Publications of Jie Han

Books and book chapters

https://www.novapublishers.com/catalog/images/9781608762262.jpg Horizons in Computer Science Research, Volume 5 http://www.crcpress.com/coverimage/?isbn=9780849396397&size=medium&flat=true http://www.crcpress.com/coverimage/?isbn=9780849396397&size=medium&flat=true

Peican Zhu, Jinghang Liang and Jie Han, "Toward Intracellular Delivery and Drug Discovery: Stochastic Logic Networks as Efficient Computational Models for Gene Regulatory Networks," a chapter in Intracellular Delivery II, Fundamental Biomedical Technologies, Volume 7, 2014, pp 327-359. Springer Netherlands: Dordrecht. (link)

Jie Han and Jose A.B. Fortes, "Reliability Analysis of Computational Structures using Nanotechnology-based Majority Logic," a chapter in Dekker Encyclopedia of Nanoscience and Nanotechnology, Second Edition. Taylor and Francis: New York, Published online: 25 Jun 2012; 1-9. (link)

Jie Han and Hao Chen, "Variation-induced Error Rate (ViER) and Variability-aware Soft Error Rate (VaSER) Analyses for Advanced CMOS Technology," a chapter in Horizons in Computer Science Research, Volume 5, August 2012, Nova Science Publishers. (book)

Jie Han and Pieter Jonker, "Computing with Superconducting Circuits of Josephson Junctions," Chapter 6 in Nanophysics, Nanoclusters and Nanodevices, 2007, Nova Science Publishers, 183-218. ISBN: 1-59454-852-8. Also in Superconductivity and Superconducting Wires (Horizons in World Physics, Volume 267), 2010. ISBN: 978-1-60876-226-2 (book)

Jie Han, Fault-Tolerant Architectures for Nanoelectronic and Quantum Devices, Universal Press, Veenendaal, The Netherlands, 2004. A Ph.D. dissertation of the Delft University of Technology, 1-135. ISBN: 90-9018888-6. (pdf)

Journals (in bold) and Conferences

2018 (Academic year when the paper was accepted or published)

Shaahin Angizi, Zhezhi He, Yu Bai, Jie Han, Mingjie Lin, Ronald F. DeMara and Deliang Fan, "Leveraging Spintronic Devices for Efficient Approximate Logic and Stochastic Neural Networks," in GLSVLSI'18, Proceedings of the 28th IEEE/ACM Great Lakes Symposium on VLSI, Chicago, IL, USA, 2018. (pdf)

Linbin Chen, Jie Han, Weiqiang Liu, Paolo Montuschi, and Fabrizio Lombardi, "Design, Evaluation and Application of Approximate High-Radix Dividers," IEEE Transactions on Multi-Scale Computing Systems, vol. PP, no. 99, pp. xxx - xxx, 2018. (pdf)

Yan Li, Yufeng Li, Jie Han, Jianhao Hu, Fan Yang, Xuan Zeng, Bruce Cockburn, and Jie Chen, "Feedback-Based Low-Power Soft-Error-Tolerant Design for Dual-Modular Redundancy," IEEE Transactions on VLSI Systems, vol. 26, no. 8, pp. 1585 - 1589, 2018. (pdf)

Yidong Liu, Siting Liu, Yanzhi Wang, Fabrizio Lombardi and Jie Han, "A Stochastic Computational Multi-Layer Perceptron with Backward Propagation," IEEE Transactions on Computers, vol. PP, no. 99, pp. xx - xx, 2018. (pdf)

Siting Liu and Jie Han, "Toward Energy-Efficient Stochastic Circuits using Parallel Sobol Sequences," IEEE Transactions on VLSI Systems, vol. 26, no. 7, pp. 1326 - 1339, 2018. (pdf)

Honglan Jiang, Leibo Liu, Fabrizio Lombardi and Jie Han, "Adaptive Approximation in Arithmetic Circuits: A Low-Power Unsigned Divider Design," Design, Automation & Test in Europe Conference (DATE 2018), Dresten, Germany, March 19-23, 2018. (pdf)

Yidong Liu, Yanzhi Wang, Fabrizio Lombardi and Jie Han, "An Energy-Efficient Stochastic Computational Deep Belief Network," Design, Automation & Test in Europe Conference (DATE 2018), Dresten, Germany, March 19-23, 2018. (pdf + complementary poster)

Xiaolong Ma, Yipeng Zhang, Geng Yuan, Ao Ren, Zhe Li, Jie Han, Jingtong Hu and Yanzhi Wang, "An Area and Energy Efficient Design of Domain-Wall Memory-Based Deep Convolutional Neural Networks using Stochastic Computing," the 19th International Symposium on Quality Electronic Design (ISQED 2018), March 13-14, 2018. (pdf)

Honglan Jiang, Leibo Liu and Jie Han, "An efficient hardware design for cerebellar models using approximate circuits," in Proceedings of the Twelfth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis Companion, Seoul, South Korea, 2017. (pdf)

Xiaogang Song, Zhengjun Zhai, Yidong Liu and Jie Han, "A stochastic approach for the reliability evaluation of multi-state systems with dependent components," Reliability Engineering and System Safety, vol. 170, no. 5, pp. 257-266, February 2018. (pdf)

Xiaogang Song, Zhengjun Zhai, Yangming Guo, Peican Zhu and Jie Han, "Approximate Analysis of Multi-State Weighted k-Out-of-n Systems Applied to Transmission Lines," Energies, 10 (11), 1740, 2017. (Open access)

2017

Michael Shoniker, Oleg Oleynikov, Bruce F. Cockburn, Jie Han, Manish Rana and Witold Pedrycz, "Automatic Selection of Process Corner Simulations for Faster Design Verification," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 37, no. 6, pp. 1312 - 1316, 2018. (pdf)

Ke Chen, Fabrizio Lombardi and Jie Han, "Partially Universal Modules for High Performance Logic Circuit Design," IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), pp. 108-111, 2017.

Xiaogang Song, Zhengjun Zhai, Peican Zhu and Jie Han, "A Stochastic Computational Approach for the Analysis of Fuzzy Systems," IEEE Access, 5, pp. 13465-13477, 2017. (pdf)

Peican Zhu, Yangming Guo, Fabrizio Lombardi and Jie Han, "Approximate Reliability of Multi-state Two-Terminal Networks by Stochastic Analysis," IET Networks, vol. 6, no. 5, pp. 116-124, September 2017. (pdf)

Peican Zhu, Yangming Guo, Shubin Si and Jie Han, "A Stochastic Analysis of Competing Failures with Propagation Effects in Functional Dependence Gates," IISE TRANSACTIONS, vol. 49, no. 11, pp. 1050 - 1064, 2017. (pdf)

Linbin Chen, Jie Han, Weiqiang Liu, Fabrizio Lombardi, "Design and operational assessment of an intra-cell hybrid L2 cache," IEEE/ACM International Symposium on Nanoscale Architectures (NanoArch'17), 2017.

Linbin Chen, Jie Han, Weiqiang Liu, and Fabrizio Lombardi, "Algorithm and Design of a Fully Parallel Approximate Coordinate Rotation Digital Computer (CORDIC)," IEEE Transactions on Multi-Scale Computing Systems, vol. 3, no. 3, pp. 139 - 151, 2017. (pdf)

Honglan Jiang, Cong Liu, Leibo Liu, Fabrizio Lombardi and Jie Han, "A Review, Classification and Comparative Evaluation of Approximate Arithmetic Circuits," ACM Journal on Emerging Technologies in Computing Systems (JETC), Vol. 13, No. 4, Article No. 60, 2017. (pdf)

Weiqiang Liu, Liangyu Qian, Chenghua Wang, Honglan Jiang, Jie Han, and Fabrizio Lombardi, "Design of Approximate Radix-4 Booth Multipliers for Error-Tolerant Computing," IEEE Transactions on Computers, vol. 66, no. 8, pp. 1435 - 1441, 2017. (pdf)

Siting Liu and Jie Han, "Hardware ODE Solvers using Stochastic Circuits," Design Automation Conference (DAC), Ariticle No. 81, 2017. (pdf)

Yuanchang Chen, Yizhe Zhu, Fei Qiao, Jie Han, Yuansheng Liu and Huazhong Yang, "Evaluating Data Resilience in CNNs from an Approximate Memory Perspective," in GLSVLSI'17, Proceedings of the 27th IEEE/ACM Great Lakes Symposium on VLSI, Banff, Alberta, Canada, 2017. (pdf)

Linbin Chen, Paolo Montuschi, Jie Han, Weiqiang Liu and Fabrizio Lombardi, "Design of Approximate High-Radix Dividers by Inexact Binary Signed-Digit Addition," in GLSVLSI'17, Proceedings of the 27th IEEE/ACM Great Lakes Symposium on VLSI, Banff, Alberta, Canada, 2017. (pdf)

Ke Chen, Jie Han and Fabrizio Lombardi, "Two Approximate Voting Schemes for Reliable Computing," IEEE Transactions on Computers, vol. 66, no. 7, pp. 1227 - 1239, 2017. (pdf)

Pilin Junsangsri, Jie Han and Fabrizio Lombardi, "Design and Comparative Evaluation of a PCM-based CAM (Content Addressable Memory) Cell," IEEE Transactions on Nanotechnology, vol. 16, no. 2, pp. 359 - 363, 2017. (pdf)

Siting Liu and Jie Han, "Energy Efficient Stochastic Computing with Sobol Sequences," Design, Automation & Test in Europe Conference (DATE), 2017. (pdf)

Yuanzhuo Qu, Jie Han, Bruce F. Cockburn, Yue Zhang, Weisheng Zhao and Witold Pedrycz, "A True Random Number Generator based on Parallel STT-MTJs," Design, Automation & Test in Europe Conference (DATE), 2017. (pdf)

Manish Rana, Ramon Canal, Jie Han and Bruce Cockburn, "SRAM Memory Margin Probability Failure Estimation using Gaussian Process Regression," IEEE International Conference on Computer Design (ICCD 2016), Phoenix, AZ, USA, October 3-5, 2016. (pdf)

Ke Chen, Fabrizio Lombardi and Jie Han, "Design and Analysis of an Approximate 2D Convolver," in IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT 2016), Sept. 19-20, 2016, University of Connecticut, USA. (pdf)

Chen Wu, Chenchen Deng, Leibo Liu, Jie Han, Jiqiang Chen, Shouyi Yin, and Shaojun Wei, "A Multi-Objective Model Oriented Mapping Approach for NoC-based Computing Systems," IEEE Transactions on Parallel and Distributed Systems, vol. 28, no. 3, pp. 662 - 676, 2017. (pdf)

Pilin Junsangsri, Fabrizio Lombardi and Jie Han, "A Non-Volatile Low-Power CAM Using Racetrack Memories," in 2016 IEEE Nanotechnology Materials and Devices Conference (NMDC), Toulouse, France, October 9-12th, 2016.

Ran Wang, Jie Han, Bruce Cockburn and Duncan Elliott, "Stochastic Circuit Design and Performance Evaluation of Vector Quantization for Different Error Measures," IEEE Transactions on VLSI Systems, vol. 24, no. 10, pp. 3169 - 3183, 2016. (pdf)

Peican Zhu, Jie Han, Yangming Guo and Fabrizio Lombardi, "Reliability and Criticality Analysis of Communication Networks by Stochastic Computation," IEEE Network, vol. 30, no. 6, pp. 70 - 76, 2016. (pdf)

2016

Pilin Junsangsri, Jie Han and Fabrizio Lombardi, "A Non-Volatile Low-Power TCAM Design Using Racetrack Memories," IEEE International Conference on Nanotechnology, Sendai, Japan, August 22-25, 2016.

Pilin Junsangsri, Jie Han and Fabrizio Lombardi, "Designs of PMC-Based Non-Volatile Memory Circuits for Data Restoring," IEEE International Conference on Nanotechnology, Sendai, Japan, August 22-25, 2016.

Honglan Jiang, Cong Liu, Naman Maheshwari, Fabrizio Lombardi and Jie Han, "A Comparative Evaluation of Approximate Multipliers," IEEE/ACM International Symposium on Nanoscale Architectures (NanoArch'16), Beijing, China, July 18-20, 2016. (Best Paper Nomination) (pdf)

Linbin Chen, Fabrizio Lombardi, Jie Han and Weiqiang Liu, "A Fully Parallel Approximate CORDIC Design," IEEE/ACM International Symposium on Nanoscale Architectures (NanoArch'16), Beijing, China, July 18-20, 2016. (pdf)

Honglan Jiang, Chengkun Shen, Pieter Jonker, Fabrizio Lombardi and Jie Han, "Adaptive Filter Design using Stochastic Circuits," in Proc. IEEE Symposium on VLSI (ISVLSI), Pittsburgh, Pennsylvania, USA, July 11-13, 2016. (pdf)

Yuanchang Chen, Xinghua Yang, Fei Qiao, Jie Han, Qi Wei and Huazhong Yang, "A Multi-Accuracy-Level Approximate Memory Architecture Based on Data Significance Analysis," in Proc. IEEE Symposium on VLSI (ISVLSI), Pittsburgh, Pennsylvania, USA, July 11-13, 2016. (pdf)

Jie Han, "Introduction to Approximate Computing," in Proc. IEEE VLSI Test Symposium (VTS), Las Vegas, NV, USA, April 25 - 27, 2016. (pdf)

Peican Zhu, Hamidreza Montazeri Aliabadi, Hasan Uludag, and Jie Han, "Identification of Potential Drug Targets in Cancer Signaling Pathways using Stochastic Logical Models," Scientific Reports, 6, 23078; doi: 10.1038/srep23078 (2016). (Open access)

Mohammad Saeed Ansari, Ali Mahani, Jie Han and Bruce Cockburn, "A Novel Gate Grading Approach for Soft Error Tolerance in Combinational Circuits," in Proc. IEEE Canadian Conference on Electrical and Computer Engineering (CCECE), Vancouver, BC, Canada, May 15 - 18, 2016. (pdf)

Peican Zhu, Jie Han, Leibo Liu and Fabrizio Lombardi, "Reliability Evaluation of Phased-Mission Systems Using Stochastic Computation," IEEE Transactions on Reliability, vol. 65, no. 3, pp. 1612 - 1623, 2016. (pdf)

Salin Junsangsri, Jie Han and Fabrizio Lombardi, "A Design of a Non-Volatile PMC-Based (Programmable Metallization Cell) Register File," in GLSVLSI’16, Proceedings of the 26th IEEE/ACM Great Lakes Symposium on VLSI, Boston, MA, USA, 2016. (pdf)

Liangyu Qian, Chenghua Wang, Weiqiang Liu, Fabrizio Lombardi and Jie Han, "Design and Evaluation of an Approximate Wallace-Booth Multiplier," in IEEE International Conference on Circuits and Systems (ISCAS 2016), Montreal, Quebec, Canada, May 22 - 25, 2016. (pdf)

Ran Wang, Jie Han, Bruce Cockburn and Duncan Elliott, "Design, Evaluation and Fault-Tolerance Analysis of Stochastic FIR Filters," Microelectronics Reliability, vol. 57, no. 2, pp. 111 - 127, 2016. (pdf)

Pilin Junsangsri, Jie Han and Fabrizio Lombardi, "Circuits for a Perpendicular Magnetic Anisotropic (PMA) Racetrack Memory," IEEE Transactions on Multi-Scale Computing Systems, vol. 1, no. 3, pp. 127 - 137, 2015. (pdf)

Jie Han, "Computing: Naturally random," Nature Nanotechnology (2015) | doi:10.1038/nnano.2015.215. (Invited) (pdf)

Linbin Chen, Jie Han, Weiqiang Liu and Fabrizio Lombardi, "On the Design of Approximate Restoring Dividers for Error-Tolerant Applications," IEEE Transactions on Computers, vol. 65, no. 8, pp. 2522 - 2533, 2016. (pdf)

Honglan Jiang, Jie Han, Fei Qiao and Fabrizio Lombardi, "Approximate Radix-8 Booth Multipliers for Low-Power and High-Performance Operation," IEEE Transactions on Computers, vol. 65, no. 8, pp. 2638 - 2644, 2016. (pdf)

Pilin Junsangsri, Jie Han and Fabrizio Lombardi, "Design of a Hybrid Non-Volatile SRAM Cell for Concurrent SEU Detection and Correction," Integration, the VLSI Journal, vol. 52, pp. 156-167, January 2016. (pdf)

Chen Zou, Weikang Qian and Jie Han, "DPALS: A Dynamic Programming-based Algorithm for Two-level Approximate Logic Synthesis," in The 11th International Conference on ASIC (ASICON 2015), Chengdu, China, 2015. (pdf)

Zhixi Yang, Jie Han and Fabrizio Lombardi, “Approximate Compressors for Error-Resilient Multiplier Design," in IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT 2015), Amherst, MA, USA, 2015. (pdf)

Salin Junsangsri, Fabrizio Lombardi and Jie Han, "Evaluating the Impact of Spike and Flicker Noise in Phase Change Memories," in IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT 2015), Amherst, MA, USA, 2015. (pdf)

Pilin Junsangsri, Fabrizio Lombardi and Jie Han, "HSPICE Macromodel of a PMA Racetrack Memory," in 2015 IEEE Nanotechnology Materials and Devices Conference (NMDC), Anchorage, Alaska, USA, September 13-16th, 2015. (pdf)

2015

Ran Wang, Jie Han, Bruce Cockburn and Duncan Elliott, "Design and Evaluation of Stochastic FIR Filters," in Proc. 2015 IEEE Pacific Rim Conference on Communications, Computers and Signal Processing, Victoria, BC, Canada, August 24 - 26, 2015. (pdf)

Ran Wang, Jie Han, Bruce Cockburn and Duncan Elliott, "Stochastic Circuit Design and Performance Evaluation of Vector Quantization," in Proc. IEEE ASAP 2015, IEEE 26th International Conference on Application-specific Systems, Architectures and Processors, Toronto, Canada, July 27 - 29, 2015. (pdf)

Zhixi Yang, Jie Han and Fabrizio Lombardi, "Transmission Gate-based Approximate Adders for Inexact Computing," IEEE/ACM International Symposium on Nanoscale Architectures (NanoArch'15), Boston, MA, U.S.A., July 8-10, 2015. (Best Paper Award) (pdf)

Ke Chen, Fabrizio Lombardi and Jie Han, "Matrix Multiplication by an Inexact Systolic Array," IEEE/ACM International Symposium on Nanoscale Architectures (NanoArch'15), Boston, MA, U.S.A., July 8-10, 2015. (pdf)

Chen Wu, Chenchen Deng, Leibo Liu, Jie Han, Jiqiang Chen, Shouyi Yin, and Shaojun Wei, "An Efficient Application Mapping Approach for the Co-Optimization of Reliability, Energy and Performance in Reconfigurable NoC Architectures," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 34, no. 8, pp. 1264 - 1277, 2015. (pdf)

Pilin Junsangsri, Jie Han and Fabrizio Lombardi, "Logic-in-Memory (LiM) with a Non-Volatile Programmable Metallization Cell (PMC)," IEEE Transactions on VLSI Systems, vol. 24, no. 2, pp. 521 - 529, 2016. (pdf)

Honglan Jiang, Jie Han and Fabrizio Lombardi, "A Comparative Review and Evaluation of Approximate Adders," in GLSVLSI’15, Proceedings of the 25th IEEE/ACM Great Lakes Symposium on VLSI, Pittsburgh, PA, USA, 2015. (pdf)

Linbin Chen, Jie Han, Weiqiang Liu and Fabrizio Lombardi, "Design of Approximate Unsigned Integer Non-restoring Divider for Inexact Computing," in GLSVLSI’15, Proceedings of the 25th IEEE/ACM Great Lakes Symposium on VLSI, Pittsburgh, PA, USA, 2015. (Best Paper Nomination - Top 4/148!) (pdf)

Pilin Junsangsri, Fabrizio Lombardi and Jie Han, "A Ternary Content Addressable Cell Using a Single Phase Change Memory (PCM)," in GLSVLSI’15, Proceedings of the 25th IEEE/ACM Great Lakes Symposium on VLSI, Pittsburgh, PA, USA, 2015. (pdf)

Chen Wu, Chenchen Deng, Leibo Liu, Shouyi Yin, Jie Han, and Shaojun Wei, "Reliability-aware mapping for various NoC topologies and routing algorithms under performance constraints," Science China Information Sciences, Vol. 58, 082401:1–082401:14, August 2015.

Ke Chen, Jie Han and Fabrizio Lombardi, "On the Restore Operation in MTJ-Based Non Volatile SRAM Cells," IEEE Transactions on VLSI Systems, vol. 23, no. 11, pp. 2695 - 2699, 2015. (pdf)

Michael Shoniker, Bruce F. Cockburn, Jie Han and Witold Pedrycz, "Minimizing the Number of Process Corner Simulations during Design Verification," Design, Automation & Test in Europe Conference (DATE 2015), Grenoble, France, March 9 - 13, 2015. (pdf)

Ke Chen, Fabrizio Lombardi and Jie Han, "An Approximate Voting Scheme for Reliable Computing," Design, Automation & Test in Europe Conference (DATE 2015), Grenoble, France, March 9 - 13, 2015. (pdf)

Leibo Liu, Chen Wu, Chenchen Deng, Shouyi Yin, Qinghua Wu, Jie Han, and Shaojun Wei, "A Flexible Energy- and Reliability-Aware Application Mapping for NoC-based Reconfigurable Architectures," IEEE Transactions on VLSI Systems, vol. 23, no. 11, pp. 2566 - 2580, 2015. (pdf)

Yu Ren, Leibo Liu, Shouyi Yin, Jie Han, and Shaojun Wei, "Efficient Fault-Tolerant Topology Reconfiguration Using a Maximum Flow Algorithm," ACM Transactions on Reconfigurable Technology and Systems, Vol. 8, No. 3, May 2015. Article No. 19. (pdf)

Naman Maheshwari, Zhixi Yang, Jie Han, and Fabrizio Lombardi, "A Design Approach for Compressor Based Approximate Multipliers," in International Conference on VLSI Design and Embedded Systems (VLSID 2015), Bangalore, India, January 3 - 7, 2015. (pdf)

Peican Zhu, Jie Han, Leibo Liu and Fabrizio Lombardi, "A Stochastic Approach for the Analysis of Dynamic Fault Trees with Spare Gates under Probabilistic Common Cause Failures," IEEE Transactions on Reliability, vol. 64, no. 3, pp. 878 - 892, 2015. (pdf)

Leibo Liu, Yu Ren, Chenchen Deng, Shouyi Yin, Shaojun Wei, and Jie Han, "A Novel Approach Using a Minimum Cost Maximum Flow Algorithm for Fault-Tolerant Topology Reconfiguration in NoC Architectures," in the 20th Asia and South Pacific Design Automation Conference (ASP-DAC 2015), Chiba/Tokyo, Japan, 2015. (pdf)

2014

Jie Han, Eugene Leung, Leibo Liu and Fabrizio Lombardi, "A Fault-Tolerant Technique using Quadded Logic and Quadded Transistors," IEEE Transactions on VLSI Systems, vol. 23, no. 8, pp. 1562 - 1566, 2015. (pdf)

Pilin Junsangsri, Jie Han and Fabrizio Lombardi, "A System-level Scheme for Resistance Drift Tolerance of a Multilevel Phase Change Memory," in IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT 2014), Amsterdam, The Netherlands, 2014. (pdf)

Linbin Chen, Fabrizio Lombardi and Jie Han, "FDSOI SRAM Cells for Low Power Design at 22nm Technology Node," IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), College Station, Texas, USA, August 3-6, 2014. pp. 527-530. (pdf)

Linbin Chen, Fabrizio Lombardi and Jie Han, "An Enhanced HSPICE Macromodel of a PCM Cell with Threshold Switching and Recovery Behavior," IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), College Station, Texas, USA, August 3-6, 2014. pp. 993-996. (pdf)

Pilin Junsangsri, Fabrizio Lombardi and Jie Han, "A Memristor-based TCAM (Ternary Content Addressable Memory) Cell," IEEE/ACM International Symposium on Nanoscale Architectures (NanoArch'14), Paris, France, July 8-10, 2014. pp. 1-6. (pdf)

Pilin Junsangsri, Fabrizio Lombardi and Jie Han, "HSPICE Macromodel of a Programmable Metallization Cell (PMC) and its Application to Memory Design," IEEE/ACM International Symposium on Nanoscale Architectures (NanoArch'14), Paris, France, July 8-10, 2014. pp. 45-50. (pdf)

Wei Wei, Kazuteru Namba, Jie Han and Fabrizio Lombardi, "Design of a Non-Volatile 7T1R SRAM Cell for Instant-on Operation," IEEE Transactions on Nanotechnology, vol. 13, no. 5, pp. 905 - 916, 2014. (pdf)

Pilin Junsangsri, Jie Han and Fabrizio Lombardi, "A Memristor-Based Memory Cell with No Refresh," IEEE International Conference on Nanotechnology, Toronto, Canada, August 18-21, 2014. (pdf)

Ke Chen, Jie Han, and Fabrizio Lombardi, "On the non-volatile performance of Flip-Flop/SRAM cells with a single MTJ," IEEE Transactions on VLSI Systems, vol. 23, no. 6, pp. 1160 - 1164, 2015. (pdf)

Peican Zhu, Jinghang Liang and Jie Han, "Gene Perturbation and Intervention in Context-Sensitive Stochastic Boolean Networks," BMC Systems Biology 2014, 8:60. (Highly accessed!)

Peican Zhu and Jie Han, "Asynchronous Stochastic Boolean Networks as Gene Network Models," Journal of Computational Biology, 21(10): 760-770, October 2014. (pdf)

Jinghang Liang, Linbin Chen, Jie Han and Fabrizio Lombardi, "Design and Evaluation of Multiple Valued Logic Gates using Pseudo N-type Carbon Nanotube FETs," IEEE Transactions on Nanotechnology, vol. 13, no. 4, pp. 695 - 708, 2014. (pdf)

Cong Liu, Jie Han and Fabrizio Lombardi, "An Analytical Framework for Evaluating the Error Characteristics of Approximate Adders," IEEE Transactions on Computers, vol. 64, no. 5, pp. 1268 - 1281, 2015. (pdf)

Wei Wei, Jie Han and Fabrizio Lombardi, "Robust HSPICE Modeling of a Single Electron Turnstile," Microelectronics Journal (Elsevier), vol. 45, no. 4, pp. 394 - 407, April 2014. (pdf)

Amir Momeni, Jie Han, Paolo Montuschi and Fabrizio Lombardi, "Design and Analysis of Approximate Compressors for Multiplication," IEEE Transactions on Computers, vol. 64, no. 4, pp. 984 - 994, 2015. (pdf)

Peican Zhu, Jie Han, Leibo Liu and Ming J. Zuo, "A Stochastic Approach for the Analysis of Fault Trees with Priority AND Gates," IEEE Transactions on Reliability, vol. 63, no. 2, pp. 480 - 494, June 2014. (pdf)

Cong Liu, Jie Han and Fabrizio Lombardi, "A Low-Power, High-Performance Approximate Multiplier with Configurable Partial Error Recovery," Design, Automation & Test in Europe Conference (DATE 2014), Dresten, Germany, March 24 - 28, 2014. (pdf + complementary poster)

Pilin Junsangsri, Fabrizio Lombardi and Jie Han, "A Hybrid Non-Volatile SRAM Cell with Concurrent SEU Detection and Correction," Design, Automation & Test in Europe Conference (DATE 2014), Dresten, Germany, March 24 - 28, 2014. (pdf)

Peican Zhu and Jie Han, "Stochastic Multiple-Valued Gene Networks," IEEE Transactions on Biomedical Circuits and Systems, vol. 8, no. 1, pp. 42 - 53, 2014. (pdf)

2013

Hao Wu, Jie Han and Fabrizio Lombardi, "A PCM-based TCAM cell using NDR," IEEE/ACM International Symposium on Nanoscale Architectures (NanoArch'13) , New York City, USA, July 15-17, 2013. (pdf)

Zhixi Yang, Ajaypat Jain, Jinghang Liang, Jie Han and Fabrizio Lombardi, "Approximate XOR/XNOR-based Adders for Inexact Computing," IEEE International Conference on Nanotechnology, Beijing, China, August 5-8, 2013. (pdf)

Ke Chen, Jie Han and Fabrizio Lombardi, "Design and Evaluation of two MTJ-Based Content Addressable Non-Volatile Memory Cells," IEEE International Conference on Nanotechnology, Beijing, China, August 5-8, 2013. (pdf)

Pilin Junsangsri, Jie Han and Fabrizio Lombardi, "On the Drift Behaviors of a Phase Change Memory (PCM) Cell," IEEE International Conference on Nanotechnology, Beijing, China, August 5-8, 2013. (pdf)

Jie Han and Michael Orshansky, "Approximate Computing: An Emerging Paradigm For Energy-Efficient Design," in ETS’13, Proceedings of the 18th IEEE European Test Symposium, Avignon, France, May 27-31, 2013. (pdf)

Yu Ren, Leibo Liu, Shouyi Yin, Jie Han, Qinghua Wu and Shaojun Wei, "A Fault Tolerant NoC Architecture Using Quad-Spare Mesh Topology and Dynamic Reconfiguration," Journal of Systems Architecture (Elsevier), Volume 59, Issue 7, Pages 482–491, August 2013. (pdf)

Yu Ren, Leibo Liu, Shouyi Yin, Qinghua Wu, Shaojun Wei and Jie Han, "A VLSI Architecture for Enhancing the Fault Tolerance of NoC using Quad-spare Mesh Topology and Dynamic Reconfiguration," in IEEE International Symposium on Circuits and Systems (ISCAS), Beijing, China, 2013.

Wei Wei, Jie Han and Fabrizio Lombardi, "Design and Evaluation of a Hybrid Memory Cell by Single-Electron Transfer," IEEE Transactions on Nanotechnology, vol. 12, no. 1, pp. 57-70, 2013. (pdf)

Jie Han, Hao Chen, Jinghang Liang, Peican Zhu, Zhixi Yang and Fabrizio Lombardi, "A Stochastic Computational Approach for Accurate and Efficient Reliability Evaluation," IEEE Transactions on Computers, vol. 63, no. 6, pp. 1336 - 1350, 2014. (pdf)

2012

J. Liang and J. Han, "Stochastic Boolean Networks: An Efficient Approach to Modeling Gene Regulatory Networks," BMC Systems Biology, 6:113, 2012. (Highly accessed!)

Jianping Gong, Jie Han, Yong-Bin Kim and Fabrizio Lombardi, "Hardening a Memory Cell for Low Power Operation by Gate Leakage Reduction," in IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT 2012), Austin, Texas, USA, pp. 73 – 78, 2012.

J. Liang, J. Han and F. Lombardi, "Analysis of Error Masking and Restoring Properties of Sequential Circuits," IEEE Transactions on Computers, vol. 62, no. 9, pp. 1694 - 1704, 2013. (pdf) (Featured on IEEE Computing Now and Transactions on Computers multimedia)

J. Liang, J. Han and F. Lombardi, "New Metrics for the Reliability of Approximate and Probabilistic Adders," IEEE Transactions on Computers, vol. 62, no. 9, pp. 1760 - 1771, 2013. (pdf)

J. Liang, L. Chen, J. Han and F. Lombardi, "Design and Reliability Analysis of Multiple Valued Logic Gates using Carbon Nanotube FETs," in IEEE/ACM International Symposium on Nanoscale Architectures, Amsterdam, The Netherlands, pp. 131-138, 2012. (pdf)

Pilin Junsangsri, J. Han and F. Lombardi, "Macromodeling a Phase Change Memory (PCM) Cell by HSPICE," in IEEE/ACM International Symposium on Nanoscale Architectures, Amsterdam, The Netherlands, pp. 77-84, 2012.

Vikas Sakode, J. Han and F. Lombardi, "Cell Design and Comparative Evaluation of a 1T Memristor-Based Memory," in IEEE/ACM International Symposium on Nanoscale Architectures, Amsterdam, The Netherlands, pp. 152-159, 2012.

W. Wei, J. Han and F. Lombardi, "Modeling a Single Electron Turnstile in HSPICE," in GLSVLSI’12, Proceedings of the 22th IEEE/ACM Great Lakes Symposium on VLSI, Salt Lake City, Utah, USA, pp. 221-226, 2012.

Jinghang Liang, Zhiyin Zhou, Jie Han and Duncan G. Elliott, "A 6.0-13.5 GHz Alias-Locked Loop Frequency Synthesizer in 130 nm CMOS," IEEE Transactions on Circuits and Systems I, vol. 60, no. 1, pp. 108-115, 2013. (pdf)

2011

J. Liang, J. Han and F. Lombardi, "On the Reliable Performance of Sequential Adders for Soft Computing," in IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT 2011), Vancouver, BC, Canada, pp. 3-10, 2011. (pdf)

H. Chen, J. Han and F. Lombardi, "A Transistor-Level Stochastic Approach for Evaluating the Reliabiltiy of Digital Nanometric CMOS Circuits," in IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT 2011), Vancouver, BC, Canada, pp. 60-67, 2011. (pdf)

N. Rajderkar, M. Ottavi, S. Pontarelli, J. Han and F. Lombardi, "On the Effects of Intra-Gate Resistive Open Defects in Gates at Nanoscale CMOS," in IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT 2011), Vancouver, BC, Canada, 2011.

W. Wei, J. Han and F. Lombardi, "A Hybrid Memory Cell Using Single-Electron Transfer," in IEEE/ACM International Symposium on Nanoscale Architectures, San Diego, CA, USA, pp. 16–23, 2011.

X. Ma, M. Hashempour, J. Han and F. Lombardi, "Modeling errors in synthesized tile sets for template manufacturing by DNA self-assembly," in IEEE Conference on Nanotechnology (IEEE-Nano), Portland, Oregon, USA, pp. 1707–1712, 2011.

J. Han, E. Boykin, H. Chen, J. Liang and J. Fortes, "On the Reliability of Computational Structures using Majority Logic," IEEE Transactions on Nanotechnology, vol. 10, no. 5, pp. 1099-1112, September 2011. (pdf)

J. Han, H. Chen, E. Boykin and J. Fortes, "Reliability evaluation of logic circuits using probabilistic gate models," Microelectronics Reliability, vol. 51, no. 2, 2011, pp. 468-476. (pdf) (One of the most cited papers in this journal in the past five years by Google Metrics and Microelectronics Reliability)

2010

H. Chen and J. Han, "Stochastic computational models for accurate reliability evaluation of logic circuits," in GLSVLSI’10, Proceedings of the 20th IEEE/ACM Great Lakes Symposium on VLSI, Providence, Rhode Island, USA, pp. 61–66, 2010. (pdf)

Pre-2010

J. Han, J. Gao, Y. Qi, P. Jonker, J. Fortes, "Toward hardware-redundant, fault-tolerant logic for nanoelectronics," IEEE Design and Test of Computers, vol. 22, no. 4, pp. 328–339, July–August 2005. (pdf)

J. Han and P. Jonker, "A defect- and fault-tolerant architecture for nanocomputers," Nanotechnology, vol. 14, no. 2, pp. 224–230, 2003. (pdf)

J. Han and P. Jonker, "A system architecture solution for unreliable nanoelectronic devices," IEEE Trans. on Nanotechnology, vol. 1, no. 4, pp. 201–208, December 2002. (pdf)

E.R. Taylor, J. Han, J.A.B. Fortes, "An Investigation into the Maximum Tolerable Error Rate of Majority Gates for Reliable Computation," IEEE International Workshop on Defect and Fault Tolerant Nanoscale Architectures (NANOARCH), 2006.

E.R. Taylor, J. Han, J.A.B. Fortes, "Towards Accurate and Efficient Reliability Modeling of Nanoelectronic Circuits," in Proc. IEEE-NANO 2006, IEEE Conference on Nanotechnology, Vol. 1, 395-398.

J. Han, E.R. Taylor, J. Gao and J.A.B. Fortes, "Faults, Error Bounds and Reliability of Nanoelectronic Circuits," in Proc. IEEE ASAP 2005, IEEE 16th International Conference on Application-specific Systems, Architectures and Processors, 247-253.

J. Han, E.R. Taylor, J. Gao and J.A.B. Fortes, "Reliability Modeling of Nanoelectronic Circuits," in Proc. IEEE-NANO 2005, IEEE Conference on Nanotechnology, 104-107.

J. Han and P. Jonker, "From Massively Parallel Image Processors to Fault-Tolerant Nanocomputers," in Proc. 17th Int. Conf. on Pattern Recognition (ICPR17), 2004, Vol. 3, 2-7.

J. Han and P. Jonker, "A Study on Fault-Tolerant Circuits using Redundancy," in Proc. VLSI 2003, Multiconference in Computer Science and Engineering, 65-69.

J. Han and P. Jonker, "Quantum Cellular Nonlinear Networks using Josephson Circuits," in Proc. IEEE-NANO 2003, IEEE Conference on Nanotechnology, 457-460.

J. Han and P. Jonker, "On Quantum Computing with Macroscopic Josephson Qubits," in Proc. IEEE-NANO 2002, IEEE Conference on Nanotechnology, 305-308.

J. Han and P. Jonker, "Novel Computing Architectures on Arrays of Josephson Persistent Current Bits," in Proc. MSM 2002, Fifth International Conference on Modeling and Simulation of Microsystems, 636-639.

J. Han and P. Jonker, "A Fault-Tolerant Technique for Nanocomputers: NAND Multiplexing," in Proc. 8th Annual Conf. of the Advanced School for Computing and Imaging, 2002, 59-66.

P. Jonker and J. Han, "On Quantum and Classical Computing with Arrays of Superconducting Persistent Current Qubits," in Proc. CAMP2000, Fifth IEEE International Workshop on Computer Architectures for Machine Perception, 2000, 69-78.

Reports

M. Forshaw, D. Crawley, P.P. Jonker, J. Han, and C. Sotomayor Torres, "Nano_Arch_Review: A Review of the Status of Research and Training into Architectures for Nanoelectronic and Nanophotonic Systems in the European Research Area," EU 6th Framework Programme Report, University College, London, UK, 2004, July, 1-36.