8 Bit ADC with build in sample and hold

by Felicia Cheng, Eric Cheung, David Li, Tin Wai Kwan


 

An analog to digital converter AD7823 by ANALOG DEVICES will be discussed in this document.
 

Reasons why this particular chip is being chosen are as following:

        1. build in track and hold function
        2. Input Supply Voltage (VDD) Range: 2.7V to 5.5V
            Reference input range: 0V to VDD
            Analog input range depends on VREF which gives more flexibility.
        3. 8 pins package which is easy to get connected to the FPGA.
        4. Low power consumption
 

Brief description of how the AD7823 works

        The serial interface of the AD7823 consists of 3 wires, a serial clock input SCLK, serial port enable CONVSTand a serial data output DOUT. The converting cycle will start when the CONVST input signal goes to high. The CONVST signal will be set back to low in order for it to have a rising edge for next cycle. Data is clocked out from the DOUT line on the first rising SCLK edge after the rising edge of the CONVST signal and on subsequent SCLK rising edges. A 1us(max) power-up time and 4.5us(max) conversion time will be needed before the first rising edge of the SCLK signal. There is also a 10ns(max) of the SCLK rising edge to DOUT Data Valid Delay. The first bit data out is the least significant bit (LSB) of the 8 bit output signal.


 
VHDL codes
 
        The vhdl codes included in this web are only for a cycle of converting one input analog sample. A input signal acknowledge ack is being sent by the main program. The CONVST will be set to high when ack is received. The serial output data are stored in a 8-bit Shift Register. Output signal data ready DataRdy will go to high when all 8 bit output from the ADC are being stored and valid. The main program should set the ack back to low to indicate the data in the shift register are no longer needed, for example after the data are being stored in another memory. The ack will be set according to the user's desired period of time. If the user wants to sample 6000 samples/sec, than the ack should be set to high every 1/6000=166us.
 

In order to get the ADC works, the following codes must be saved and compiled in your own directory.
The codes must be compiled in the the following orders:

1. ADC_pkg.vhd
    - ADC_pkg includes all the components need for the ADC interfacing

2. DFlip.vhd
    - DFlipFlop is a 1 bit register which is needed for the shift register.
    - for there is max 10 ns of the SCLK rising edge to DOUT Data Valid Delay, process is being taken with the falling edge of the clk

3. shReg.vhd
    - with ADC7823, a 8 bit shift register is needed
    - If you needed a different number of bit of a shift register, this shift register can be reused by changing the generic.

4. clk_divider.vhd
    - this specific clock divider is only for doubling up the clock period of the input clock.
    - if you need a clock divider with a different output clock period, clk_divider1.vhd will be useful.

5. ADC.vhd
    - ADC.vhd will be controlled by the main program, which will send the input signal ack to the ADC.vhd.
    - ADC.vhd program will then send the appropriate signal at the appropriate time to the ADC chip, in order for it to get the correct output.

6. ADCcontroller.vhd
    - this program will control the number of samples in a sec.
 

reference

Analog Device AD7823 datasheet