--------------
-- DFlip.vhd
-- D- FLIP FLOP
-- falling edge of the clock is used to input signal 
--------------

library IEEE;
use IEEE.std_logic_1164.all;


entity DFlip is
	port (	Qin:	in std_logic;
			clk:	in std_logic;
			rst:	in std_logic;
			load:	in std_logic;
			Qout:	out std_logic );
end DFlip;


---- A single bit D flip flop
---- a behavioral representation 

architecture behavior of DFlip is
begin
	process (rst, clk)
	begin
		if rst = '0' then
			Qout<='0';
		elsif (clk = '0' and clk'event) then	-- load data when falling edge
			if load = '1' then
				Qout<=Qin;
			
			end if;
		end if;
	end process;
end behavior;