------------------------
-- file clk_divider.vhd
------------------------
-- the clock from the FPGA is 25.175MHz, ~40ns
-- in this program, the clock will be slow down to half the speed
-- output clock period ~80ns
------------------------

library ieee;
use ieee.std_logic_1164.all;

library work;
use work.ADC_pkg.all;

entity clk_divider is
	port (
		clkin: in std_logic;
		clkout: out std_logic
		);
end clk_divider;

architecture speeddown of clk_divider is

signal inclk : std_logic := '0';

begin
clkout <= inclk;
process(clkin)

begin

	if rising_edge(clkin) then
		inclk <= not inclk;
	end if;

end process;
end speeddown;