------------------------
-- file clk_divider1.vhd
------------------------
-- the clock from the FPGA is 25MHz, 40ns
-- in this program, the output clock period will be slow down according to the divisor
--  clkout = divisor*2*clkin
--	e.g. when clkin = 40ns  
-- 		@divisor = 1  => clkout = 80ns
--				 = 2  => clkout = 160ns
--				 = 12500000  => clkout = 1sec
------------------------

library ieee;
use ieee.std_logic_1164.all;

library work;
use work.ADC_pkg.all;

entity clk_divider1 is
	generic( divisor: positive:=2);
	port (
		clkin: in std_logic;
		clkout: out std_logic;
		rst: in std_logic);
end clk_divider1;

architecture speeddown of clk_divider1 is

signal inclk: std_logic:= '0';

begin

clkout <= inclk;

process(clkin, rst)

variable count:natural range 0 to divisor; 

begin

	if (rst = '0') then
		count:=0;

	elsif rising_edge(clkin) then
		count:= count+1;
		if count = divisor then
			inclk <= not inclk;
			count := 0;
		end if;
	
	end if;
end process;

end speeddown;