--------------------------
-- ee552 project
-- ADC interfacing
-- shReg.vhd
---------------------------
-- this is a 8 bit register which used to store the 8 bit data out from the ADC
-- serial input and parallel output
-- controlled by load, clock, and reset
-- modified from my own original register from ee480
---------------------------

library ieee;
library work;
use ieee.std_logic_1164.all;
use work.ADC_pkg.all;

entity shReg is
	generic ( reg_width: positive:=8);
	port (	input:	in std_logic;
			load:	in std_logic;
			clk:	in std_logic;
			rst:	in std_logic;
			output:	out std_logic_vector(reg_width-1 downto 0));
end shReg;

-- structural of regist

architecture behavioral of shReg is

signal inreg : std_logic_vector(reg_width downto 0);

begin

	inreg(0) <= input;
	
	gen: for I in 0 to reg_width-1 generate
		DF:  DFlip port map(
			Qin => inreg(I),
			load => load,
			clk => clk,
			rst => rst,
			Qout => inreg(I+1)
		);
	end generate;

	--parallel output	
	gen2: for N in 0 to reg_width-1 generate
		output(N)<=inreg(N);
	end generate;

end behavioral;