RAM vs. Data Registers
Kim Ellis & Mark Kudryk
October 28, 1998
If you ever wondered when to use RAM or when to use Data Registers, here's a little comparison.
GOAL:
The goal was to have 10 8-bit signals originating in one module available for another module, plus have the data known within the sending module.
The second module is set up to only receive one data signal at a time, in both cases. The first module can either know it's own data, as used in the data registers, or retrieve it one at a time, as in the RAM.
DATA REGISTERS IMPLEMENTATION:
To simplify the number of interconnecting wires between modules, a multiplexer was used to channel the data into one 8-bit signal. The registers are implicitly implemented within the first module, simply by having each data signal as an output from the module. This also ensures that the first module has it's own data available to itself.
The following diagram is a picture representation of the data register implementation.
Added is a link to the register-multiplexer VHDL code (registers.vhd).
RAM IMPLEMENTATION:
The RAM implementation was divided into a control path and a data path. Since both modules will be requesting to access RAM, a memory controller was designed using a Moore state machine. Priority was given to the second module in this case.
The complete memory interconnection looks like the following:
For reference, the VHDL code for the Ram implementation is included (memory.vhd).
Each module needs an outgoing request line, an incoming acknowledge line, their own read/write line, plus the address line (named code# here). The memory controller state machine is the following:
Included is a link to the VHDL code for the state machine (memcntrl.vhd).
LPM_RAM_DQ was used to implement the RAM block.
COMPARISION:
|
DATA REGISTERS |
RAM |
|
Total I/O pins used: 86/183 ( 46%) |
Total I/O pins used: 26/183 ( 14%) |
|
Total logic cells used: 82/1152 ( 7%) |
Total logic cells used: 11/1152 ( 0%) |
|
Total embedded cells used: 0/48 ( 0%) |
Total embedded cells used: 8/48 ( 16%) |
|
Total EABs used: 0/6 ( 0%) |
Total EABs used: 1/6 ( 16%) |
As can be seen from the Altera's fitter, the number of logic cells is higher when implementing the 16-to-1 multiplexer, versus the memory controller state machine used for the RAM implementation.
Also the number of pins (or data lines) is much reduced by implementing the RAM solution.
RECOMMENDATIONS:
If the number of signals are at a minimum, the data register solution will work, and is a much less complex solution.
On the other hand if the number of signals is on a larger scale, the RAM solution is much more "elegant" and reduces the logic cell count. Also, if the RAM blocks are not being used within the design, it would free up logic cells to use the RAM to store variables which are shared between modules.