-- The Electronic Gardener
--
-- Mark Kudryk, Kim Ellis
--
-- Module Name:  registers.vhd
-- Author COPYRIGHT: Kim Ellis
-- Date: October 28, 1998
----------------------------------------------------------------------------
-- Description:
--   To transfer data from one module to another. Implementing a data register
--   format with a multiplexer. 10 8-bit signals are channeled down to one
--   8-bit output
----------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;

entity registers is
    port( sel                   : in std_logic_vector( 3 downto 0 );

          d0, d1, d2, d3, d4,
          d5, d6, d7, d8, d9    : in std_logic_vector( 7 downto 0 );

          dataout               : out std_logic_vector( 7 downto 0 )  );
end registers;
-------------------------------------------------------------------
architecture a of registers is
begin
    process(sel, d0, d1, d2, d3, d4, d5, d6, d7, d8, d9)
    begin
        case sel is
            when "0000" =>
                dataout <= d0;
            when "0001" =>
                dataout <= d1;
            when "0010" =>
                dataout <= d2;
            when "0011" =>
                dataout <= d3;
            when "0100" =>
                dataout <= d4;
            when "0101" =>
                dataout <= d5;
            when "0110" =>
                dataout <= d6;
            when "0111" =>
                dataout <= d7;
            when "1000" =>
                dataout <= d8;
            when "1001" =>
                dataout <= d9;
            when others =>
                dataout <= (others=>'0');
        end case;
    end process;
end a;