-- The Electronic Gardener
--
-- Mark Kudryk, Kim Ellis
--
-- Module Name:  memory.vhd
-- Author COPYRIGHT: Kim Ellis
-- Date: October 28, 1998
----------------------------------------------------------------------------
-- Description:
--   To transfer data from one module to another. Implemented using lpm_ram_dq
--   and a Moore state machine memory controller. 8-bit signals are stored in
--   RAM 
----------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
library lpm;
use lpm.lpm_components.all;

entity memory is
    port(  clk                          : in    std_logic;
           reset                        : in    std_logic;
           req1, req2, rw1, rw2         : IN	STD_LOGIC;
           code1, code2                 : IN	STD_LOGIC_VECTOR( 3 downto 0 );
           ack1, ack2                   : OUT	STD_LOGIC;
           datain                       : in    std_logic_vector( 7 downto 0 );
           dataout                      : out   std_logic_vector( 7 downto 0 ) );
end memory;

architecture structure of memory is
    signal signal_we : std_logic;
    signal signal_address : std_logic_vector( 3 downto 0 );

    component memcntrl IS
        PORT(  clk                          : IN	STD_LOGIC;
               reset                        : IN	STD_LOGIC;
               req1, req2, r_w_1, r_w_2     : IN	STD_LOGIC;
               code_1, code_2               : IN	STD_LOGIC_VECTOR( 3 downto 0 );
               ack1, ack2                   : OUT	STD_LOGIC;
               we                           : OUT	STD_LOGIC;
               address                      : OUT	STD_LOGIC_VECTOR( 3 downto 0 ));
    END component memcntrl;

begin

    memory_control : memcntrl
        port map( clk     => clk,
                  reset   => reset,
                  req1    => req1,
                  req2   => req2,
                  r_w_1   => rw1,
                  r_w_2  => rw2,
                  code_1  => code1,
                  code_2 => code2,
                  ack1    => ack1,
                  ack2   => ack2,
                  we      => signal_we,
                  address => signal_address);                  
                  
    mem_cell: lpm_ram_dq
         generic map(  lpm_width    => 8,
                       lpm_widthad  => 4,
                       lpm_outdata  => "UNREGISTERED")
         port map(  data     =>  datain,
                    address  =>  signal_address,
                    we       =>  signal_we,
                    inclock  =>  clk,
                    q        =>  dataout);

end structure;