Student Contributed Documentation

Useful VHDL Code - Digital Clock

As many people are going to use a digital clock in their design, we would like to post our VHDL code out so that others can use it.

There are two VHDL entities for the digital clock.
- set_time.vhd is for setting the current time.
- inc_time.vhd is for incrementing the clock.
Here, we assume that there is a set_time button. When the user press on the button, i.e. set_time is high, the user can then set the current time. At the same time, the clock will stop incrementing and resume only after the user has finished setting the time.
We assume the clock frequency is 250 HZ for simulation purpose. You can change it to whatever value you want and you just need to remember to change the value of count at the same time. But keep in mind that for higher clock frequency, the number of modules will also increase.
set_time has 151 modules while inc_time has 151 modules.