-- increment time -- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; -- Commenting out the Actel library --library asyl; --use asyl.arith.all; -- reset is to initialize the inc_time -- diff_m is to indicate that user has set minute -- diff_h is to indocate that user has set hour -- min_in is the input minute from the set_time -- hr_in is the input hr from the set_time -- min_out is the output of the current minute -- hr_out is the output of the current hour entity inc_time is port( reset, clock, diff_m, diff_h : in std_logic; min_in : in std_logic_vector(5 downto 0); hr_in : in std_logic_vector(4 downto 0); min_out : out std_logic_vector(5 downto 0); hr_out : out std_logic_vector(4 downto 0) ); end inc_time; architecture behaviour of inc_time is signal minute: std_logic_vector(5 downto 0) := "000000"; signal hour: std_logic_vector(4 downto 0) := "00000"; begin INC :process(clock, diff_m, diff_h) variable m: std_logic_vector(5 downto 0) := "000000"; variable h: std_logic_vector(4 downto 0) := "00000"; type time_count is range 0 to 250; variable count: time_count:=0; begin if rising_edge(clock) then if reset = '1' then count := 0; m := "000000"; h := "00000"; minute <= "000000"; hour <= "00000"; elsif reset = '0' then if diff_m = '1' then m := min_in; minute <= m; end if; if diff_h = '1' then h := hr_in; hour <= h; end if; if diff_m = '0' and diff_h = '0' then count := count + 1; end if; if (diff_m = '0' and diff_h = '0' and count = 250) then count := 0; if m < "111011" then m := m+'1'; minute <= m; elsif m = "111011" then m := "000000"; minute <= m; if h = "10111" then h := "00000"; hour <= h; else h := h + '1'; hour <= h; end if; end if; end if; end if; end if; end process INC; min_out <= minute; hr_out <= hour; end behaviour;