-- increment time
--

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

-- Commenting out the Actel library
--library asyl;
--use asyl.arith.all;

-- reset is to initialize the set_time
-- t_fwd is use to increment (synchronous)
-- t_bck is use to decrement (synchronous)
-- min: the minute
-- hr: the hour
-- h_light is use to indicate that it is setting the hour
-- m_light is use to indicate that it is setting the minute

entity set_time is
	port(
		reset, set, clock	: in std_logic;
		t_fwd	: in std_logic;
		t_bck	: in std_logic;
		min	: out std_logic_vector(5 downto 0);
		hr	: out std_logic_vector(4 downto 0);
		h_light	: out std_logic;
		m_light, enable : out std_logic
	);
end set_time;

architecture behaviour of set_time is


signal state	:std_logic_vector(1 downto 0):="00";
signal next_state	:std_logic_vector(1 downto 0);

begin

mode		:process(state)
	
	begin
	   case state is
	   	when "11"=> next_state <= "10";	     
	   	when "10"=> next_state <= "01";	   					
	   	when "01"=> next_state <= "11";		   		
		when "00"=> next_state <= "10";
	   	when others => NULL;
	   end case;
	 
	 end process mode;  
	   
	   
n_state	:process(clock,set,reset)	
	begin
		if rising_edge(clock)then
			if reset = '1' then
				state <= "00";
			elsif reset = '0' then
				if set = '1' then
					state <= next_state;
				end if;
			end if;
		end if;
	end process n_state;	   

change		:process(t_fwd, t_bck, state,clock)
	variable m1: std_logic_vector(5 downto 0);
	variable h1: std_logic_vector(4 downto 0);
	begin
	if rising_edge(clock) then
	  case state is
	  	when "00" =>
			m1 := "000000";	
			h1 := "00000";
		when "01" =>
		   	if t_fwd = '1' then
			  if m1 /= "111011" then
				m1 := m1+'1';
			  else
				m1 := "000000";
			  end if;
		   	elsif t_bck = '1' then
		  	  if m1 = "000000" then
		  		m1:="111011";
		  	  else
		  		m1:= m1-'1';
		  	  end if;
		   	end if; 
		when "10" =>
		   	if t_fwd = '1' then
			  if h1 /= "10111" then
				h1 := h1+'1';
			  else
				h1 := "00000";
			  end if;
		   	elsif t_bck = '1' then
		  	  if h1 = "00000" then
		  		h1:="10111";
		  	  else
		  		h1:= h1-'1';
		  	  end if;
		   	end if;
		 when others => NULL;
	  end case; 
	  min <= m1;
	  hr <= h1;
	end if;
	end process change;

h_light <= state(1) and (not state(0));
m_light <= (not state(1) and state(0));
enable <= (state(1) and (not state(0))) or (not state(1) and state(0));


end behaviour;