This keypad interface code is a radical departure
from the keypad code from the code found in the existing application notes
where hybrid Moore/Mealy machines or seperated next state/current state/output
logic are implemented. These application notes were used as a starting
point in the design although the implemented code is significantly different.
This was because the hybrid state machine architectures did not perform
well when implemented on the Altera FPGAs. This code, although significantly
longer than previous keypad code, is written in full accordance with the
state machine template inside MAXPLUS2.
The keypad decoder used a common row and column-scanning
algorithm. The state machine began by driving all of the columns to a low
value and detecting if any of the rows, which are weakly pulled high with
4.7k resistors, were driven to zero. If any one row was driven to zero,
that would mean that a key was depressed. The state machine will then wait
several clock cycles for the keypad-bouncing transients to die down and
then proceed to determine which key was pressed. It does this by shifting
a zero through each column while keeping the other columns high. When it
detects a zero in a particular row, the intersection of the column driven
to zero and the row that has a zero as its input will yield the desired
key. The keyscanning routine then waits for the key to be released by driving
all the columns to 0 and waiting for all of the rows to go high. The keyscanning
routine then starts from the beginning. The resulting keypress is latched
to an output register where the value is held until another keypress is
detected. Furthermore, the keyvalid signal will go high for 1 clock period
following the detection of a valid keypress. The recorded keyvalue can
be output to a hexadecimal to 7-segment decoder on the UP1 development
board. The code for the seven segment decoder as well as the necessary
components and a top-level keytesting program are included.
Links to the VHDL files
aysnc_counter.vhd
keydecode.vhd
registern.vhd
VHDL package
Test file for keydecode
Package for use with keytest.vhd
led.vhd