Application Note
VHDL Implementation of a Serial Peripheral Interface (SPI)

Authors: Andrew Chu and Chris Ohlmann
Group: The Reading Book
Other Group Members: Jeff Bazinet, Reid Blumell, Bryce Palmer

Serial Peripheral Interface

The Serial Peripheral Interface (SPI) is a high speed (up to 400 Mhz) synchronous serial interface/protocol designed by Motorola. It is a popular interface used for connecting peripherals to each other and to microprocessors. Most literature indicates that the interface can only be used for eight or sixteen bit block data transfers, but many Motorola microcontrollers allow transfers of any range of blocks between two and sixteen bits at a time. Because of the serial nature of the interface, data transfers of more than sixteen bits at a time can be implemented easily through control signals.

The interface uses a 3-wire bus plus a chip/slave select line for each device connected to the bus. The three bus lines are as follows:

Each device connected to the bus can be selected by the bus master using a dedicated SS (Slave Select) line for each slave device. It is possible to have more than one master hanging off the bus, but only one master can be active at any given time. The implication of this configuration is that the bus master has to have as many lines as there are devices to drive each of the SS lines.

When the master initiates a data transfer, the master writes a bit to the MOSI line and reads a bit from the MISO at the same time on every cycle of the SCLK signal. The data is transfered through a simple shift register transfer scheme where the data is clocked into and out of devices on a first-in, first-out basis. This means that every data transfer results in an exchange of bits between the master and the slave (each device is simultaneously a transmitter and a receiver), making it a full duplex serial interface. When a device is not selected, it must tri-state (release) the output (MISO) line. Through buffering, it would be possible to drive more than one receive-only device, but not more than one transmit-only or receive and transmit device since there would be a contention issue on the MISO line.

The block diagram of this process is as follows:

There are four possibilities for clocking the data based on the clock polarity and the clock phase:

Usually, in synchronous serial protocols, data is clocked out on one edge and clocked in on the other edge to reduce clock skew errors.

Advantages of SPI

Disadvantages of SPI

Alternatives to SPI

VHDL Implementation

Layer 1 protocol implementation usually involves implementing a PHY (Physical layer interface) and a MAC (Media Access Controller). The following sample implementation follows this design philosophy:


Implemented as a simple shift register: spi_phy.vhd


Provides a parallel interface to a higher layer with appropriate control signals. This controller loads the PHY with the parallel data and sends out n clock pulses, where n corresponds to the number of bits in the parallel data, to the PHY to clock the transfer: spi_controller.vhd