----------------------------------------------------------------------
-- SPI_CONTROLLER
----------------------------------------------------------------------
-- This entity passes device driver data to and from the SPI_PHY.  It
-- also initializes the clock to synchronize transmission on the bus.
----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;

entity SPI_Controller is
generic
(
	data_width : positive := 8
);
port
(
	clock : in std_logic;

	-- Device Driver Interface Signals
	ready : in std_logic;
	load, done : out std_logic;
	driver_tx_data : in std_logic_vector(data_width-1 downto 0);
	driver_rx_data : out std_logic_vector(data_width-1 downto 0);

	-- SPI Bus Control Signals
	SCLK : out std_logic;
	bus_tx_data : out std_logic_vector(data_width-1 downto 0);
	bus_rx_data : in std_logic_vector(data_width-1 downto 0)
--	SS : out std_logic_vector(num_devices-1 downto 0)
);
end entity SPI_Controller;


architecture mixed of SPI_Controller is

	TYPE STATE_TYPE IS (wait_for_ready, set_SCLK_high, 
						set_SCLK_low, finished);
	SIGNAL state, next_cycle: STATE_TYPE;

begin

	bus_tx_data <= driver_tx_data;
	driver_rx_data <= bus_rx_data;

	Process_Transmission : process(clock) is
		variable count : integer;
	begin
		IF ready = '0' THEN
			load <= '1';
			SCLK <= '0';
			done <= '0';			
			state <= wait_for_ready;
		ELSIF rising_edge(clock) THEN
			CASE state IS
				-- Load Shift Registers and Prepare for Transmission
				WHEN wait_for_ready =>
					count := 0;
					state <= set_SCLK_high;

				-- Initialize Clock (one extra clock added for loading data)
				WHEN set_SCLK_high =>
					SCLK <= '1';
					-- Check if all data bits have been sent
					IF count = data_width THEN
						next_cycle <= finished;
					-- If data bits remain send the next bit
					ELSE
						count := count + 1;
						next_cycle <= set_SCLK_high;
					END IF;
					state <= set_SCLK_low;

				-- Inform Controller Transmission is complete
				WHEN finished =>
					done <= '1';

				-- Pull SCLK Low to Complete Clock Cycle
				WHEN set_SCLK_low =>
					SCLK <= '0';
					load <= '0';
					state <= next_cycle;

			END CASE;
		END IF;
		
	end process;

end architecture mixed;