Introduction

This document briefly introduces the IEEE 802.3u MII standard and provides fully functional VHDL source code for interfacing with an MII-based transceiver. While the provided code could potentially be used in a 100 Mb/s implementation, a few minor changes would have to be made.  This design has only been simulated and physically tested at 10 Mbit/s.

Medium-Independent Interface (MII) is the IEEE standard interface between the MAC (controller) and PHY (transceiver) layers of a 100 Mbit/s Ethernet implementation, defined in the IEEE 802.3u standard.  It is a 4-bit wide parallel interface.
 

Signals

The MII standard defines the following signals:
 

Signal	Input/Output (from MAC's perspective)	Purpose
MDIO	I/O	Serial control line used to set/read internal register values in the MII compliant transceiver.
MDC	O	Control line clock. All transitions on MDIO are synchronous to this clock signal. This clock must run no faster than 2.5 MHz.
RXD[3 downto 0]	I	nibble-wide data read by the MAC layer on the rising edge of RXCLK.
RXDV	I	Indicates when data on RXD is valid.
RXCLK	I	Clock signal, either 2.5 or 25 MHz (10/100 Mbit, respectively) provided by PHY.  All RXD transitions  are synchronous to this clock.
RXER	I	Defined for 100 Mbit/s transmission only.  Indicates certain types of errors in receive stream.
TXER	O	Defined for 100 Mbit/s transmission only.  Forces generation of error in transmit stream. See IEEE 802.3u for a more complete description.
TXCLK	I	Clock signal, either 2.5 or 25 MHz (10/100 Mbit, respectively) provided by PHY.  All TXD transitions are synchronous to this clock.
TXEN	O	Enables transmission of the nibble appearing on TXD[3 downto 0].
TXD[3 downto 0]	O	nibble-wide data read by PHY on rising edge of TXD.
COL	I	Defined in half-duplex mode only.  Indicates a collision was detected by PHY.
CRS	I	Carrier Sense. Indicates that the physical Ethernet medium is busy.

Note that no guarantees are made about the phase relationship between TXCLK and RXCLK.

All the above signals, save MDIO, MDC, RXER, and TXER are defined as inputs or output to the Ethernet module provided below.  RXER and TXER are not needed for a 10 Mbit/s implementation.  MDIO and MDC are not needed in a minimal implementation (such as the one provided in the Ethernet module below) because the transceiver registers have convenient default values.  The Ethernet module instantiates various components defined in eth_pkg.vhd.
 

Receiving Data

The 802.3u standard indicates that the data received on the RXD[3 downto 0] data lines is properly bit-aligned, meaning that each 4-bit nibble is either the lower 4 bits or upper 4 bits of a transmitted byte of data. The lower 4 bits are received first, then the upper 4 bits. For example, if the following nibbles (in hexadecimal) were received: "8", "9", "A", "B", the bytes transmitted were "0x98" and "0xBA".

The format of Ethernet frames is described in an earlier student application note. Essentially, the frame begins with 15 consecutive "0101" preamble nibbles, followed by a "1101", then the data. The MII standard does not specify how many of the 15 preamble nibbles will appear at RXD[3 downto 0]. In order to receive data, the MAC must wait for RXDV to be high and RXD[3 downto 0] to be "1101". The nibble after "1101" is the first valid data nibble. Specifically, it is the low 4 bits of the first byte of the destination MAC address of the Ethernet frame. Refer to the previously mentioned student application note for more information on the Ethernet frame format.
 

Transmitting Data

Data appearing on the TXD[3 downto 0] lines is transmitted when TXEN is high. The least significant 4 bits should be sent before the most significant 4 bits for each byte. To transmit 0xB8, for example, the nibble "8" should be sent, then "B".

Before any data can be sent, the MAC is responsible for first transmitting a valid preamble and start-of-frame delimiter (15 x "0101" + "1101"). In order for the Ethernet frame to be valid, TXEN must remain high for the entire duration of the frame, which means the data appearing at TXD[3 downto 0] must be ready on every TXCLK cycle (400ns clock period).
 

Ethernet Module

The Ethernet module that we wrote provides an even simpler interface to an MII transceiver. The intention of our module is to provide transceiver input/output synchronisation, byte-wide communication, and preamble generation.

Signals

The Ethernet module has two sets of signals, the MII signals and the internal interface signals. The MII signals used are a subset of those described in the standard, because for most Ethernet implementations, some of the signals are unnecessary. The MII signals we use and the corresponding VHDL signal name are given below:
 

MII Signal	VHDL Signal
RXCLK	rxclk
RXDV	rxdv_4
RXD[3 downto 0]	rxdata_4(3 downto 0)
TXCLK	txclk
TXEN	txen_4
TXD[3 downto 0]	txdata_4(3 downto 0)
COL	col

The signals provided to the designer are the following:
 

VHDL Signal	Description
clk	System clock. Must be 2.5 Mhz for proper 10Mbit operation, or 25MHz for 100 Mbit operation.
reset	Active high asynchronous reset
sync_clk	Synchronising clock, used to synchronise rxclk and txclk to the system clock, clk. Should be 10x the frequency of the system clock
rxdv	Indicates a byte of data is ready to be read
rxdata(7 downto 0)	Byte of received data
txen	When this signal first goes from low to high, a preamble is generated and transmitted. 8 byte times later, bytes are read from txdata(7 downto 0) and transmitted. Transmission ceases when txen goes low.
txdata(7 downto 0)	Byte of data to be transmitted
drop	Indicates the current frame should be dropped.

These signals are all clocked on the clk signal, with the exception of the asynchronous reset and the synchronisation clock.

An important limitation of the ethernet module is that bytes must be sent only every second clock cycle. This is simply because Ethernet transmission is only 4 bits/clk, so bytes can be transmitted only every 2 clock cycles.
 

Code
 

File	Description
eth_pkg.vhd	The VHDL package that contains all components of the Ethernet module
ethernet.vhd	Top-level ethernet entity
receiver.vhd	Handles reception of Ethernet frames, takes 4-bit nibbles and constructs 8-bit bytes
transmitter.vhd	Handles transmission of Ethernet frames, including generation of preamble/start-of-frame-delimiter. Accepts bytes and transmits nibbles.
sync.vhd	Synchronises all MII signals to the system clk
sub_sync.vhd	Used by sync to synchronise a set of signals between 2 distinct clocks of the same frequency/period