-------------------------------------------------------------------------------

-- sub_sync
-- -------
-- Synchronizes 1 4 bit vector + 1 additional bit between 2 clock domains
-- of equal frequency with the help of a faster sync_clk
--
-- Authors: Jeffrey Spiers
--          Colin Durocher
--          Richard Mao
--          Angela Wong
--
-- Modifications
-- -------------
-- 03/05/01 Colin		Created
-------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;


entity sub_sync is
	port(
		-- 2 slow clocks, 1 fast sync_clk used to sync up slower guys
		clk_in, clk_out, sync_clk:	in std_logic;
		-- clear state
		clr:						in std_logic;
		-- data we read
		data_in:					in std_logic_vector(3 downto 0);
		-- data we write
		data_out:					out std_logic_vector(3 downto 0);
		-- data_valid signal we read
		dv_in:						in std_logic;
		-- data_valid signal we write
		dv_out:						out std_logic
	);
end entity sub_sync;


ARCHITECTURE behavioural OF sub_sync IS
	TYPE STATE_TYPE IS (idle, got1_clk1, got1_clk2, stall, update);
	SIGNAL state: STATE_TYPE;
	signal data_in_reg:	std_logic_vector(3 downto 0);
	signal dv_in_reg:		std_logic;
BEGIN

	-- receive inputs synchronous to input clock
	get_inputs: process(clk_in, clr)
	begin
		if clr = '1' then
			data_in_reg <= (others => '0');
			dv_in_reg <= '0';
		elsif rising_edge(clk_in) then
			data_in_reg <= data_in;
			dv_in_reg <= dv_in;
		end if;
	end process get_inputs;

	-- sync state machine uses the fast synchroniser clock
	state_machine: PROCESS (sync_clk, clr)
	BEGIN

		IF clr = '1' THEN
			state <= idle;
			dv_out <= '0';
		ELSIF sync_clk'EVENT AND sync_clk = '1' THEN
			CASE state IS

				WHEN idle =>
					IF clk_in = '1' THEN
						state <= got1_clk1;
					END IF;			
		
				WHEN got1_clk1 =>
					IF clk_out = '1' THEN
						state <= got1_clk2;
					END IF;

				WHEN got1_clk2 =>
					state <= stall;

				WHEN stall =>
					state <= update;

				WHEN update =>
					data_out <= data_in_reg;
					dv_out <= dv_in_reg;
					state <= idle;

			END CASE;
		END IF;
	END PROCESS;


END behavioural;