Ethernet Physical Implementation

Contents

  1. Abstract
  2. Isolation Transformers
  3. Filters and Physical Layer Decoder
  4. Schematic
  5. Data Format
  6. VHDL Bitstream Decoder Example
  7. Glossary
  8. References / Resources

Abstract

This Application Note details a specific physical implementation of ethernet that has been tested and is known to produce a simple and reliable interface to a 10Base-T network.

Isolation Transformers

The ethernet specification for twisted wire pairs (10Base-T) indicates that data is transmitted as a differential signal; the common mode voltage is not known to the stations connected to the pair.  Thus, each station must be electronically isolated from the twisted pair through isolation transformers to prevent damage.  Special transformer packages have been developed to fit these transformers into a single chip package.  The one that was chosen for our project was manufactured by Halo Electronics (Distributor: Davetek Marketing, Calgary).

Halo Electronics makes a series of isolation transformers and filter circuits tuned to individual ethernet physical layer ICs.  The ML2653 (see below) was chosen as our physical layer device, and has built in filters, so the plain isolation transformer package was chosen, the TG62-1006N1 (SOIC package.  A DIP package is available, but we were unable to get samples.)  The package was connected as shown in the schematic.

Filters and Physcial Layer Decoder

Filtering and Decoding of the packets takes place inside an ethernet physical layer IC.  We chose the ML-2653 from MicroLinear Devices (Distributor: Insight Electronics , Calgary).  The ML-2653 (PLCC or TQFP package) is an ethernet physical layer chip, designed to support a variety of controllers.  For the purposes of our project, a raw bitstream was desirable, so the ML-2653 was used on its own without a controller chip.

The ML-2653 provides a receive enable signal (RxE) that indicates when data is being received by the chip.  Data is provided on the receive data (RxD) line, clocked by the receive clock (RxC).  There are several different formats for the receive data selected by inputs CS0-CS2.  The value we chose (and which is shown in the schematic below) is highlighted in the table below [1]:
 
 
CS2-0 TxC TxE RxC RxE Col Lpbk Idle RxC Idle RxD
000 R H R H H H On data + 5 extra '0'
001 F L F L L L On data only '1'
010 R H R H H H On data only '1'
011 F H R H H L Continuous '0'
(Taken from ML2653 DataSheet)[1]

The table shows the various configurations available by selecting the CS2-0 lines.  'R' denotes data is clocked on the rising edge of the respective clock (TxC = transmit clock, RxC = receive clock) while 'F' indicates data is clocked on the falling edge.  'H' indicates the signal is active high, 'L' indicates the signal is active low.  RxC can be provided only when data is incoming (ie. Each edge of RxC corresponds to a valid data bit).  Another alternative is to provide an extra 5 clock cyles to allow data to flow through any pipelines preset.  The last alternative is to have RxC available continuously, although that makes determining the start of the packet problematic (assertation of RxE is several clock cycles ahead of start of data.  See [1] for more information.

Note that the ML2653 also provides pull-downs on the /XMT and /LINK pins to power two LEDs, for link status and activity detection.  This is handled internally to the chip and no control is provided, but they are useful debugging tools.  The LEDs should be biased with 510 Ohm resistors as shown in the schematic.

Schematic

Our implementation was connected as follows.  The diagram is slightly modified from the Application Circuit in the ML2653 datasheet

Data Format

A raw bitsteam is provided for each packet by the ML2653.  To use the data, the frame (described in [3]) must be stripped from the packet.  The code provided assumes the configuration shown in the table above was chosen.

VHDL Bitstream Decoder Example

The sample code come in two pieces: a low level receiver that converts the serial bit stream (Clocked on rising edge of RxC)into an 8-bit parallel byte stream clocked on the master clock with data valid signals (ethernetreceiver.vhd), and a high level receiver that strips the frame from the data, and provides some rudimentary error checking (ethernetRX.vhd).  The state machine in the high level routine is structured to allow for easy insertion of MAC address comparators or a CRC generator, as FPGA resources allow.
 
ethernetreceiver.vhd                        Converts serial stream to parallel stream
ethernetRX.vhd                                Strips ethernet fram from data

Glossary

SOIC : Small Outline Integrated Circuit.  A common package for surface mount chips with a small number of pins. See [2] for more information.

DIP : Dual Inline Package.  An older IC packaging technology for ICs with few pins. See [2] for more information.

PLCC : Plastic Leaded Chip Carrier.  A common package for chips with a small number of pins.  Sockets can be purchased that allow wire wrap or soldering easily. See [2] for more information.

TQFP : Thin Quad Flat Pack.  A common package for chips with a large number of pins.  Fine spacing between pins, difficult to solder, best used on a printed circuit board. See [2] for more information.

References/Resources

[1] ML2653 DataSheet
[2] Integrated Circuit Package Identification: Shows the various packages.
[3] Ethernet Overview: An overview of the frame format

MicroLinear Products Page
Halo Electronics Products Page
 


Author: Rob Behm
Last Update: 25 March, 2001