---------------------------------------------------
-- Ethernet Receiver
--
-- Takes an ethernet bitsream coming in serially, and 
-- converts it to eight bit bytes.  A complete discussion
-- of the data formats is made in ethernetRX.vhd the high level file for 
-- the ethernet interface
--
-- EE 552 Spring 2001
-- Rob Behm (Author)
-- Craig Joly
-- Wendy Benbow

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity ethernetreceiver is
	port (
		reset 	: in std_logic;			-- Active high reset
		master_clock : in std_logic;		-- 25.175 MHz master clock
			
		RxC			: in std_logic;		-- 10Mhz Receive clock, from 2653      
		-- Enable signal, indicating packet transmission
		RxE			: in std_logic;		
		-- Serial data from ethernet physical layer
		RxD			:	in std_logic;
		-- data output, 8 bits wide
		data_in : buffer std_logic_vector(7 downto 0);
		-- indicates valid data on data_in
		data_valid: out std_logic
		);
end ethernetreceiver;

architecture vhdl of ethernetreceiver is
-- Component declaration for shift register created in MaxPlus2 
-- Megafunctions.  This is an 8-bit left shift register
component ethernetshiftin IS
	PORT
	(
		clock		: IN STD_LOGIC ;
		enable		: IN STD_LOGIC ;
		shiftin		: IN STD_LOGIC ;
		sclr		: IN STD_LOGIC ;
		q		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
	);
END component;

-- Pipeline for incoming data
signal data_sample : std_logic_vector (7 downto 0);
-- Counter to count eight bits ofdata
signal count : std_logic_vector (3 downto 0);

begin
	-- Instance of the shift register
	shiftreg : ethernetshiftin 
		port map (
			enable => RxE,
			clock => RxC,
			shiftin => RxD,
			sclr => reset,
			q => data_sample);
			
	-- This process takes the data from the shift register every eight
	-- bits and stores it in a register, for transmission to data_in
	sample : process (RxC, RxE, reset)
	begin
	if reset = '1' then
			data_in <= "00000000";
			count <= "1000";
	elsif rising_edge(RxC) then
				if count = "0000" then
					count <= "0111";
					data_in <= data_sample;
				else
					count <= count - 1;
					data_in <= data_in;
				end if;						
		end if;
	end process sample;
	
	-- This process generates a data_valid signal after each
	-- byte is loaded into data_in.  This is done by looking at the
	-- raising the data_valid line while the fifth bit of the current
	-- packet is being processed, to give the downstream application
	-- time to receive the signal and smaple the data.
	datav : process (master_clock)
	variable old_data : std_logic;
	begin
		if rising_edge(master_clock) then
			if reset = '1' then
				old_data := '0';
			end if;
			if count = "0101" then
				if old_data = '0' then
					data_valid <= '1';
					old_data := '1';			
				else
					data_valid <= '0';
				end if;
			else
				old_data := '0';
				data_valid <= '0';
			end if;
		end if;
	end process;

end vhdl;