TestBenches Using File I/O under VHDL
Last updated 2000 03 06
Contributors:
Details:
In simulating complex digital systems, it is sometimes important to test
boundary cases using arbitrary test input. This style of testing is known as
testbenching. We have found it very useful to implement testbenches using
text files with testing data. The following outlines what is required to make a VHDL
testbench using the file I/O method.
Step 1:
Create the VHDL entity that you wish to test bench.
Step 2:
Compile this entity under MaxPlus II, and extract the timing information.
Step 3:
Create test data by hand for boundary cases and place the set into a
text file OR randomly create test data via Python/Perl or any other language to
feed into a text file. See this for a sample Python
script to generate random data.
Step 4a:
Create the testbench VHDL. Ensure that the testbench has only lines
like Reset and Clock in the port declaration that don't require testing at
different values. In the architecture declaration of the VHDL testbench,
ensure that all lines that you wish to randomly initiate have signal
declarations. Assign these test signals and testbench port signals
to the VHDL entity port map that you are creating a testbench
for.
Step 4b:
Now make sure that you add use std.textio.all; in
the library declaration section of your testbench VHDL.
Now use the following text I/O functions to input/output your test data into the
VHDL:
-- this allows you to open a test vector file
file vector_file : text is "vectorfilename";
-- this opens a file for output data.
-- note: text is "name" is the same as declaring text open read_mode is "name" by default.
file out_file : text open write_mode is "vectors.out";
-- returns a 1 if at the end of a file, 0 otherwise.
endfile(vector_file)
-- creates a textline variable that can hold a line of
text
variable textline : line;
-- reads an entire line of text into the textline variable
readline(vector_file,textline);
-- reads the next value on the textline that
fits the type of testinteger
read(textline,testinteger);
-- write the string value
into the line type outline
write(outline,String'(" this is a testbench "));
-- this outputs the contents of outline into
the textfile defined by out_file
writeline(out_file,outline);
A completed sample test bench for lab5 (pipelined adder), click
HERE.
Step 5:
The testbench must be run from Mentor Graphics. I recommend initially
testing the test bench and the component soly under Mentor Graphics, without
using the extracted timing information from Max Plus II. This simulates
substantially faster.
The commands to execute the test bench in the Mentor Graphics simulator are:
restart -force
force reset 1 0, 0 80
force clock 0 0, 1 40 -repeat 80
run -a
The first resets the simulation, the second generates a reset pulse and
third creates an infinite clock. The run command will run the simulation
until the program aborts by calling assert with a failure severity.
The waveforms this produces can be seen by setting up the waveform viewer
before running the test bench.
Please e-mail the authors with any inaccuracies.