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-- File based testbench for the adder VHDL
-- This testbench reads in numbers from a file and passes them into the 
-- adder component for calculation. It then compares the output of the adder
-- module with the expected value from the vector file and writes the results
-- of the add to an output file. Any mismatches are flagged with an assertion.

library ieee; 
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library std;
use std.textio.all;
use work.adder;

entity testbench is
  generic(adder_width : positive := 56);
  port (clock, reset : in std_logic);
end entity testbench;

architecture behavioral of testbench is
   signal a,b : std_logic_vector(adder_width-1 downto 0);
   signal sum : std_logic_vector(adder_width downto 0);
   signal dataout_valid, datain_request : std_logic;
   signal datain_valid, dataout_request : std_logic;

   component adder
      port(a, b : in std_logic_vector(adder_width-1 downto 0);
           clock, reset, datain_valid, dataout_request : in std_logic;
           dataout_valid, datain_request : out std_logic;
           sum : out std_logic_vector(adder_width downto 0));
   end component adder;

begin

   -- The adder component we are testing
   add: adder port map(a => a,
                       b => b,
		       clock => clock,
		       reset => reset,
		       datain_valid => datain_valid,
		       dataout_request => dataout_request,
		       dataout_valid => dataout_valid,
		       datain_request => datain_request,
		       sum => sum);
   
   test: process 
      file vector_file : text is "vectors";
      file out_file : text open write_mode is "vectors.out";
      variable oL,L : line;
      variable Pa, Pb, Ps : integer;
      variable good_number : boolean;
      variable Result : std_logic_vector(sum'range);
   begin      
      -- Loop over the file      
      while not endfile(vector_file) loop
         datain_valid <= '0';
         dataout_request <= '0';
	 
         -- Wait for a clock to synchronize the loading of a and b
         wait until rising_edge(clock) and (reset = '0');

         -- Read in the 3 numbers, if the first number is valid then
	 -- assume the entire line is correct
         readline(vector_file,L);
	 read(L,Pa,GOOD => good_number);

         -- End of file, tell the simulator to stop.
         if not good_number then
   	    assert good_number report "Stopped" severity failure;
	 end if;
	 
	 -- Convert the numbers to bit vectors and assign them to the inputs
	 -- and expected outputs. This can only handle 16 bit numbers, to do
	 -- more the numbers would have to be expressed in binary in the file 
	 a <= std_logic_vector(TO_UNSIGNED(Pa,a'length));
	 read(L,Pb);
	 b <= std_logic_vector(TO_UNSIGNED(Pb,b'length));
	 read(L,Ps);
	 Result := std_logic_vector(TO_UNSIGNED(Ps,Result'length));
       	
	 -- Now run the adder, the sequence is.. wait for datain_request
	 -- set datain_valid for 1 cycle, lower datain_valid, set dataout_request
	 -- wait for dataout_valid
	 wait until rising_edge(clock) and (datain_request = '1');
         datain_valid <= '1';
	 wait until rising_edge(clock);
         datain_valid <= '0';
         dataout_request <= '1';
	 wait until rising_edge(clock) and (dataout_valid = '1');
         dataout_request <= '0';
	 
	 -- Write to the output file the results of the add.
	 if sum /= result then
	    write(oL,String'("Mismatch: "));
	 end if;
	 
	 write(oL,String'("a="));
	 write(oL,Pa);
	 write(oL,String'(" b="));
	 write(oL,Pb);	 
	 write(oL,String'(" Res="));
	 write(oL,Ps);
	 write(oL,String'(" Got="));
	 write(oL,TO_INTEGER(UNSIGNED(sum(16 downto 0))));
	 -- Write to the sceen: writeline(output,oL);
	 writeline(out_file,oL);
			   
	 -- Compare the sum with the result and log errors
	 assert (sum = result) report "Not matching";
      end loop;
   end process;
   
end behavioral;