Design
There are major components to the system:
- Audio microphone
- Analog Amplifiers
- Sample and Hold
- A/D converter
- FPGA Control
Stages 1 and 2 don't need any explanation at this time, but the reason for stage 3 does. The A/D converter requires it's input value to be held constant over it's conversion cycle. For our A/D (ADC0809) this can be as long at 100us. For our circuit the inputs can change over 100us hence we can not assume constant inputs. The sample and hold circuit takes a sample and can then maintain that constant value over a much longer period. In this circuit our sample time is 1.5us and hold time is ~100us. This provides stage 4 with valid inputs.
Microphone
The
microphone used for this circuit was a condenser type. This means it
requires current to function. The microphone itself has an internal
resistance of 2k ohms, but
since we lacked the spec sheet for the mic could only guess at it's
current requirements. We initially assumed a >1mA requirement and
hence used a 1k resistor. Using an oscilloscope you can measure Vout.
With a small amount of fiddling, trying different R values, we found
that for this mic a value of 10K produced the strongest (highest
gain) at Vout. With a 10k resistor this is about 0.5mA flowing
through the microphone.
Amplifier
Amplification was done using 2 separate stages, a pre-amp and final amplification. Two stages were used to avoid oscillations and non-ideal operation amplifier characteristics when very high gain (10000-1000000 times) configurations. Both amplifier stages are built using an LM324 single ended op amp. This allows for a single power supply of 5 volts to drive the amplifier system. This does limit the positive output from the op-amp to 4.2 volts, but this upper limit can then be corrected for in the A/D section.
Pre-Amplifier
The
pre-amplification stage provides the main source of gain for the
amplifier. Once the signal is then amplified the second stage
amplifier provides a variable (10-100 times) amplification that can
be used for volume control. The op-amp configuration used is an
inverting single ended amplifier biased at Vcc/2. The circuit is
given in the LM324 application notes. Both Ccouple and C2 are 10uF
electrolytic capacitors which were salvaged from prior labs, they
provide DC blocking and a signal ground respectively. The gain for
the amplifier is given by 110k/250 = 440.
Amplifier
The
setup for the last amplifier stage is very similar to to pre-amp with
the exception of the gain. The input 250 ohm resistor is replaced
with Rvar a 1-10k ohm pot. This allows the user to adjust the
microphone sensitivity. Finally output was verified with an
oscilloscope and set such that whistling would saturate the output
when the mic was held about a foot from the mouth. Whistling was very
easy for this mic to pick up and provided a strong
consistent wave form.
Sample and Hold
The sample and hold (S&H) circuit provides the A/D converter with a stable value over a long period which was sampled from a rapidly changing input. The sample time and hold characteristics are given by charts on the specification sheets for the S&H chip. For the SMP-11GY we used the optimum value of 5000pF. This allows for a sample time of 0.75uS (90% input) on a signal with a maximum of 5 volt swing. For safety we will given the S&H twice the time, 1.5us. Since the A/D takes 100us to do a conversion the extra 0.75us will not be a major impact on performance.
There are a couple of important notes about the SMP11 that need to be mentioned. The chip requires at least +-12V supply to operate. While not explicitly stated in the spec sheet the S&H does not turn on until 4.5Volts and does not perform satisfactorily until the +-12V range. This means that a dual rail supply will be required to operate this circuit. If this is a major concern, you may wish to find another S&H circuit as opposed to what's readily available from the parts room.
The input for the A/D say the maximum input voltage is Vcc + 0.3V, since the S&H can output +-12V at full swing two protection diodes are used from clamp the output between Vcc+Vdiode and Gnd-Vdiode.
The sample/hold input is worth mentioning. The signal must be low for hold and high for sample. Control for it is done through the FGPA
The SMP11 has two nulling input offsets, they were never connected since no major voltage offsets were seen at the output.
A/D Converter
An Analog Devices ADC0809 was used to perform the A/D conversion. It's a slow speed 8 bit A/D with 8 analog inputs with a MUX to select which input is converted and a tri-state output stage. The outputs are the 8 data lines, a conversion done signal (EOC); inputs are the analog input signals, input selection, start conversion(SOC), output enable, address latch enable, and clock. The input clock can be within 640kHz to 1.2Mhz, and a conversion is done in 100 clock cycles after the fall of start of conversion. Data inputs must be steady from the rise of start of conversion until the conversion done signal is raised.
The schematic is:
The
tristate-output is tied active since the outputs are fed directly to
the FPGA and not used in a bus configuration. The input mux is not
require so the input selection is fixed at 000, and input 0 is used.
Address latch enable is tied active since the 3 select lines do not
vary, and hence don't need to be latched at a set value.
FPGA
Now that the external circuit is capable of providing a digital version of the mic input, we need the FPGA to control the circuit and read the data. This was done using 2 entities. The first was a generic power of 2 clock divider. The clock divider provides the input clock into the A/D. A division ratio of 32 was used to provide a 790kHz clock. The second is a state machine to read the data, EOC and provide SOC and Sample signals.
The structure of the state machine is not very complicated, though there are a couple of points worth mentioning:
EOC does not drop once SOC goes high. EOC may even be high as many as 1 clock cycle after SOC goes low. Hence the extra wait cycles in the state machine.
Once EOC returns high the analog inputs can start changing again, hence the read cycle is also use to start the sample cycle. This provides additional time for the S&H to acquire the current value.
The data is clocked through two sets of registers to allow for the shift/skew in the two different clocks. The first set of registers loads the data based on the slow clock. The second stage of registers loads the data from the first stage based on the system clock. This helps ensure that he data is always valid to output stages running on the system clock.
The clock divider is available is here and the digital control here.