LIBRARY ieee;
USE ieee.std_logic_1164.all;

LIBRARY work;

ENTITY input_reader IS
	generic ( ad_bits : positive := 8 );
	port (
		clock : IN STD_LOGIC;
		slow_clock : IN STD_LOGIC;  -- 640kHz clock
		reset : IN STD_LOGIC;
		end_of_conv : IN STD_LOGIC;  -- Convertion done from a/d -- input since we set it to 1 under start to restart machine
		sample : OUT STD_LOGIC;  -- Connects to sample input on sample and hold
		bits  : IN STD_LOGIC_VECTOR(ad_bits - 1 downto 0); -- Input bits from the a/d
		data_out : OUT STD_LOGIC_VECTOR(ad_bits - 1 downto 0); -- Cleaned and clocked internal inputs
		start_of_conv : OUT STD_LOGIC -- Start of convertion to a/d and sample of 
	);

END input_reader;

ARCHITECTURE a OF input_reader IS
	TYPE STATE_TYPE_CONV IS (sample_conv, start_conv, in_conv, in1_conv,end_conv, read_conv);
	SIGNAL next_state, state: STATE_TYPE_CONV;
	
	SIGNAL hold_out : STD_LOGIC_VECTOR(ad_bits - 1 downto 0);
BEGIN
	PROCESS (slow_clock)
	BEGIN
		IF reset = '1' THEN
			next_state <= sample_conv;
		ELSIF slow_clock'EVENT AND slow_clock = '1' THEN
			start_of_conv <= '0'; -- start of convertion is normally 0
			sample <= '0';
			CASE state IS
				WHEN sample_conv =>
					sample <= '1';
					next_state <= start_conv;
				WHEN start_conv =>
					start_of_conv <= '1';
					next_state <= in_conv;
				WHEN in_conv =>
					IF end_of_conv = '0' THEN -- Wait until end of convertion goes to 0 (should be 1 clock cycle after start goes low)
						next_state <= in1_conv;
					END IF;
				WHEN in1_conv =>
					IF end_of_conv = '1' THEN -- Wait until end of convertion comes high
						next_state <= end_conv;
					END IF;
				WHEN end_conv =>
					next_state <= read_conv; -- one wait state at end of convertion
				WHEN read_conv =>
					hold_out <= bits;
					sample <= '1';  -- start sampling, inputs can change EOC is high
					next_state <= sample_conv;
			END CASE;
		END IF;

	state <= next_state;

	END PROCESS;


	fifo: PROCESS(hold_out)
	BEGIN
		WAIT UNTIL rising_edge(clock);
		data_out <= hold_out;
	END PROCESS fifo;
END a;