For our EE552 project, we design an alarm clock. Here are some useful things which we use in our design.
For those of your who may need a 24 hour clock for your projects, to make your life easier here is VHDL code to implement a 12 hour clock with and am/pm indicator. This can probably save you many hours of work. 24 hr Clock
Suppose that we want to perform certain functions only once at the falling edge of a signal, whose period is much longer than that of the clock, but we are not able to because we also need to detect the rising edge of the clock (it is not allowed to have more than one event in one "if" statement). What we can do is to implement a latch. Suppose we want to perform some functions at the falling edge of a signal called "pm" and the rising edge of "slow_clock", we declare a signal, say "latched", as a local signal of type Boolean. We can write the state machine as follows. latch
Here is a neat way to improve large schematic capture diagrams with lots of wire connections. Using Design Architect in the gen_lib there are two components called offpag.in and offpag.out. Connecting these two components to your input and output respectively and giving them the same name is exactly like connecting them together with wires. This is very useful for large schematics to avoid cluttering and making your schematic easy to read. In many cases it is also a quicker method of putting your schematics together.