24 Hour Clock Code

--Project  "The Smart Alarm Clock"
--File name: Time_display.vhd

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;		
use ieee.std_logic_unsigned.all;	

entity time_display2 is
	generic ( num_width : positive :=4 ); 
	port ( slow_clock : in std_logic;
	       am_pm_in, time_set, reset : in std_logic;
	       am_pm_out	  : out std_logic;
	       num1_bcd_out, num2_bcd_out, num3_bcd_out, num4_bcd_out : buffer std_logic_vector ( num_width - 1 downto 0)
	      );
end time_display2;



architecture order of time_display2 is 
	
		begin
		--this process is where the normal clock operation takes place
		--I chose to use compounded if statements so that I would not have a large number of 
		--states,  althouth this is not the method I would normally use I found it to be most appropriate
		--because otherwise if state maps were used there would be 1440 states to deal with and this would be to combersome
		show : process(slow_clock)
		variable count : natural := 0;
		begin
			
			if slow_clock = '1' and slow_clock'event then	--resets to a known state 12:00
				if reset = '1' then
					num1_bcd_out <= "0000";
					num2_bcd_out <= "0000";
					num3_bcd_out <= "0010";
					num4_bcd_out <= "0001";
					am_pm_out <= '0';
					count:= count + 1 ;
					if count = 120 then		-- 120 for a clock of 2 Hz.
						if num1_bcd_out = 9 then
							num1_bcd_out <= "0000";	--resets minutes back to 0 when minutes are 9
							if num2_bcd_out = 5 then
								num2_bcd_out <= "0000";	--resets minutes back to 0 when minutes are 59
								if num3_bcd_out = 9 then	--sets time to 10:00 when its 9:59
									num3_bcd_out <= "0000";
									num4_bcd_out <= num4_bcd_out + '1';
								elsif num3_bcd_out = 2 and num4_bcd_out =1 then		--resets back to 1 o'clock when it's 12:59
									if am_pm_in = '0' then
										am_pm_out <= '1';
									elsif am_pm_in = '1' then
										am_pm_out <= '0';
									end if;
									num3_bcd_out <= "0001";
									num4_bcd_out <= "0000";
								else 
									num3_bcd_out <= num3_bcd_out + '1';
								end if;
							else
								num2_bcd_out <= num2_bcd_out + '1';
							end if;
						else
							num1_bcd_out <= num1_bcd_out + '1';
						end if;
					count := 0;
					end if;
				
			end if;
		end process show;
end order;