The following is a summary of the parameters and usage of the lpm_ram_io module:

VHDL Port and Generic Defenition:

COMPONENT lpm_ram_io
   GENERIC (LPM_WIDTH: POSITIVE;
      LPM_TYPE: STRING := LPM_RAM_IO;
      LPM_WIDTHAD: POSITIVE;
      LPM_NUMWORDS: STRING := UNUSED;
      LPM_FILE: STRING := UNUSED;
      LPM_INDATA: STRING := REGISTERED;
      LPM_ADDRESS_CONTROL: STRING := REGISTERED;
      LPM_OUTDATA: STRING := REGISTERED);
   PORT (address: IN STD_LOGIC_VECTOR(LPM_WIDTHAD-1 DOWNTO 0);
      we: IN STD_LOGIC;
      inclock: IN STD_LOGIC := '1';
      outclock: IN STD_LOGIC := '1';

      outenab: IN STD_LOGIC := '1';
      memenab: IN STD_LOGIC := '1';
      dio: INOUT STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0));
END COMPONENT;

LPM_WIDTH (required)

Width of data[] and q[] ports.

LPM_WIDTHAD (required)

Width of the address port.

LPM_NUMWORDS

Size of memory in "words". The default (ie. when not specified) is 2^LPM_WIDTHAD.

LPM_FILE

Name of the Memory Initialization File (.mif) or Hexadecimal (Intel-Format) File (.hex) containing the inital values in the RAM. The default is null (ie. zreo-blanked).

LPM_INDATA

"REGISTERED" or "UNREGISTERED". Specifies whether the signal on the data port (dio) must be latched in by a rising edge on inclock or outclock (registered), or is immediately used in the memory operation (unregistered). The default is "REGISTERED" (Best to leave it like this).

LPM_ADDRESS_CONTROL

"REGISTERED" or "UNREGISTERED". "UNREGISTERED" means the address[], memenab, and we ports have immediate effect. "REGISTERED" means they only take effect on the rising edge of inclock. Registered mode is the default, and is recommended.

LPM_OUTDATA

"REGISTERED" or "UNREGISTERED". Specifies whether the output data must be latched by a rising edge on outclock before it appears at the data (dio) port (registered), or immediately apperas on the dio port after a memory operation (unregistered). The default is "REGISTERED" (Best to leave it like this).

address[] (required)

Address port (LPM_WIDTHAD bits wide).

we (required if "inclock" is not used)

Active-high Write Enable input. The memory location is overwritten by the signal on the data port (LPM_INDATA="UNREGISTERED") or the value last latched in from the data port (LPM_INDATA="REGISTERED"). The functionality of WE (rising-edge sensitive or active high level-sensitive) is determined by the paramtere LPM_ADDRESS_CONTROL.

inclock (optional but recommended)

The clock signal used to latch in signals on the data port during syncronous write operations. To perform a syncronous write, the data and address ports are set up, WE is brought high, and the actual write operation occurs on the rising edge of inclock. If outclock is not used, the write operation is controlled only by the WE signal (asynchronous operation).

outclock (optional but recommended)

The clock signal used to latch the data read from memory onto the q port (synchronous read operation). If this signal not used, the data appears "immediately" on the q port when the address changes (asynchronous read operation)

memenab (required if outenab is not present)

Memenab enables the tri-state data (dio) port. The dio port is tri-stated (disabled) when memenab is low. Memenab should be low when the signal on the address bus is changing.

outenab (required if memenab is not present)

Either outenab or memenab must be present. Outenab controls the direction of the dio port. A high signal makes dio an output port for memory read operations. A low signal allows the dio port to take input for read operations

dio[] (required)

Data input/output (LPM_WIDTH bits wide).

Typical Operation