The following is a summary of the parameters and usage of the lpm_ram_dq module:

VHDL Port and Generic Defenition:

COMPONENT lpm_ram_dq
   GENERIC (LPM_WIDTH: POSITIVE;
      LPM_TYPE: STRING := L_RAM_DQ;
      LPM_WIDTHAD: POSITIVE;
      LPM_NUMWORDS: STRING := UNUSED;
      LPM_FILE: STRING := UNUSED;
      LPM_INDATA: STRING := REGISTERED;
      LPM_ADDRESS_CONTROL: STRING := REGISTERED;
      LPM_OUTDATA: STRING := REGISTERED);
   PORT (data: IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0);
      address: IN STD_LOGIC_VECTOR(LPM_WIDTHAD-1 DOWNTO 0);
      we: IN STD_LOGIC := '1';
      inclock: IN STD_LOGIC := '1';
      outclock: IN STD_LOGIC := '1';
      q: OUT STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0));
END COMPONENT;

LPM_WIDTH (required)

Width of data[] and q[] ports.

LPM_WIDTHAD (required)

Width of the address port.

LPM_NUMWORDS

Size of memory in "words". The default (ie. when not specified) is 2^LPM_WIDTHAD.

LPM_FILE

Name of the Memory Initialization File (.mif) or Hexadecimal (Intel-Format) File (.hex) containing the inital values in the RAM. The default is null (ie. zero-blanked).

LPM_INDATA

"REGISTERED" or "UNREGISTERED". Specifies whether the signal on the (input) data port must be latched in by a rising edge on inclock (registered), or is immediately used in the memory operation (unregistered). The default is "REGISTERED" (Best to leave it like this).

LPM_ADDRESS_CONTROL

"REGISTERED" or "UNREGISTERED". "UNREGISTERED" means the signal on the data port is written to the location on the address port as soon as WE is brought high. "REGISTERED" means the data is written to the specified address when WE is high and a rising edge occurs clock. BE CAREFUL that the DATA AND ADDRESS PORTS ARE STABLE when WE is brought high and "UNREGISTERED" is used, or the memory could be corrupted with transient values. The default is "REGISTERED" (It's probably a good idea to leave it in the default setting).

LPM_OUTDATA

"REGISTERED" or "UNREGISTERED". Specifies whether the output data must be latched by a rising edge on outclock before it appears at the output data (q) port (registered), or immediately appears on the q port (unregistered). The default is "REGISTERED" (Best to leave it like this).

data[] (required)

Data input port (LPM_WIDTH bits wide).

address[] (required)

Address port (LPM_WIDTHAD bits wide).

we (required if "inclock" is not used)

Active-high Write Enable input. The memory location is overwritten by the signal on the data port (LPM_INDATA="UNREGISTERED") or the value last latched in from the data port (LPM_INDATA="REGISTERED"). The functionality of WE (rising-edge sensitive or active high level-sensitive) is determined by the paramtere LPM_ADDRESS_CONTROL.

inclock (optional but recommended)

The clock signal used to latch in signals on the data port during syncronous write operations. To perform a syncronous write, the data and address ports are set up, WE is brought high, and the actual write operation occurs on the rising edge of inclock. If outclock is not used, the write operation is controlled only by the WE signal (asynchronous operation).

outclock (optional but recommended)

The clock signal used to latch the data read from memory onto the q port (synchronous read operation). If this signal not used, the data appears "immediately" on the q port when the address changes (asynchronous read operation)

q[] (required)

Data output (LPM_WIDTH bits wide).

Typical Operation