This page is dedicated to Mentor Graphics and help with VHDL and QHSim.

Student Contributed Documentation

This is an integrated tutorial of how to use Mentor Graphics QHSIM, qvhcom and Design Architect environments with Actel's FPGA development tools.(Mike and Ishfaqur)

In order to help people to get through all those CAD tools quickly, a short tutorial providing a step-by-step procedure from using Design Architect, Actmapw to Designer is given. Check out the title page for links to bugs and their workarounds and some useful VHDL code. (Cheong and Norman)

Tips on how to produce synthesizable code and even some pieces of code which you can use, clock generators in particular. (Ka Wing and Norah)

Here is some vhdl code for a BCD to 7 segment LED converter. You may also want to check out this code for creating TTL style logic entities. (Anco and John)

If you need some help and general good advice setting up and using Design Architect, check out the page. (Quentin and Aaron)

Other Documentation

The Mentor Graphics home page may be of some help. At the very least you can take your complaints right to the top.