-- BASIC ACT1 LIBRARY COMPONENTS
-- written by Anco Snip / John Forcadas
-- This code can belong to the category of work arounds.
-- When we converted the schematics to VHDL the resulting code will use
-- library act1;
-- However, we had problems using this library with actmap so
-- we made behavioral descriptions of all the components.

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

entity NAND2 is
	port( A, B : in std_logic; Y : out std_logic);
end NAND2;
architecture structure of NAND2 is
	begin
		Y <= not (A and B);
end structure;

library ieee;
use ieee.std_logic_1164.all;

entity MX2 is
	port( A, B, S: in std_logic; Y: out std_logic);
end MX2;
architecture mux1 of MX2 is
	begin
		process(S, A, B)
			begin
			if(S ='0') then
				Y <= A;
			else
				Y <= B;
			end if;
		end process;
end mux1;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

entity INV is
	port( A : in std_logic; Y: out std_logic);
end INV;
architecture struct of INV is
	begin
		Y <= not A;
end struct;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

--buffer is implemented using two inverters in series !
entity BUFF is
    port(A : in std_logic; Y : out std_logic) ;
end BUFF;
architecture buffer1 of BUFF is
	component INV
		port( A : in std_logic; Y: out std_logic);
	end component;
		
	for all: INV use entity work.INV(struct);
	signal connect: std_logic;
	begin
		inv1: INV port map(A =>A,  Y => connect);
		inv2: INV port map(A => connect, Y => Y);
end buffer1;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

entity OA1 is
        port(A, B, C : in std_logic; Y : out std_logic) ;
end OA1;
architecture behav of OA1 is
	begin
		Y <= (A or B) and C;
end behav;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

entity DF1 is
      port(D, CLK : in std_logic; Q : out std_logic) ;
end DF1;
architecture behave of DF1 is
	begin
		process(CLK)
			begin
				if (CLK='1' and CLK'event) then
					Q <= D;
				end if;
		end process;
end behave;           

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

entity DF1A is
        port(D, CLK : in std_logic; QN : out std_logic) ;
end DF1A;
architecture dflip of DF1A is
	begin
		process(CLK)
			begin
				if (CLK='1' and CLK'event) then
					QN <= not D;
				end if;
		end process;
end dflip;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

entity DFC1 is
      port(D, CLK, CLR : in std_logic; Q : out std_logic) ;
end DFC1;
architecture behave of DFC1 is
	begin
		process(CLK, CLR)
			begin
				if (CLR='1') then
					Q <='0';
				elsif (CLK='1' and CLK'event) then
					Q <= D;
				end if;
		end process;
end behave;