Written by Dan Kotylak and Adrian Chan
| Bug | Fix/Workaround |
|---|---|
| Actel Actmap "ERROR: Internal Error..." |
One cause is having an underscore "_" in your pathname (ie any directory above the current one with a "_" character in it). If this is the case, Actmap seems to have a problem reading the .edn file that is created by some calls to Actgen. This causes the compilation to fail. |
| Instantiating Actel VHDL components | You can use Actel library components by declaring the appropriate
components in your code and then instantiating them with a port
map statement. Actmap will recognize these components during
compilation. The format of the VHDL components can be found at:
|
| Actel Designer - problem with multiple clock signals | This causes a problem when you are using the ACT1 family (ACT1 has only
1 clock network).
When Actmap compiles your VHDL code, it automatically inserts input, output, and clock buffers. Sometimes it thinks it sees more than 1 clock. This seems to occur when an external pin is connected directly to a "clock" pin on an internal entity (anything that is named clock, clk, etc.). We fixed this problem by instantiating an INBUF component and connecting the offending input to it. This forces Actmap to use an INBUF instead of a CLKBUF. |
| Design Architect - problems opening .vhd source files. |
This problem arises when you are using Actel tools and compile your designs into the directory where your .vhd files are located. Specifically, the .edn, .edo, and *.als_edn_data.attr seem to confuse da. To fix the problem, when using Actmap compile your files into a separate directory. |
| Can't synthesize 4-bit counter |
Actmap seemed to have problems synthesizing counters that are 4-bits wide. This problem showed up in the form of various compile errors from Actmap. We fixed this by using a wider counter. |
| Problems finding Actel libraries in back-annotation | We had problems (like everyone else) with VHDL back-annotated simulation.
Specifically, Design Architect had problems finding the Actel libraries
when compling the structural VHDL code (generated from .edn or .edo
file with edn2vhdl). We got around this by compiling our code by using
the command line complier qvhcom instead of da's compiler.
To use qvhcom you must have a quickhdl.ini file in your current directory. You can create this by using qhmap to map the Actel libraries. You also cannot have the MGC_WD and QUICKHDL variable set (ie open a new shell). When the above conditions are met, you will be able to compile your structural VHDL. Compilation might also work in da, but we did not try this. Further documentation can be found in /opt1/actel/doc/manuals.pdf |