EE 552 2002w 2002-1-18
Lab 2: VHDL for Synthesis
In this lab, you will write a behavioural description of a design in VHDL,
suitable for synthesis.
Detailed directions for Mentor Graphics tools are given. You will
need to be able to use Mentor Graphics for later labs and the project.
Mentor Graphics also has a command line interface, which you are welcome
to use.
This lab has two parts: an exercise that is not handed in, in which
you will become familiar with the tools, and a lab that will be submitted
for marking, in which you will create your own design.
Labs are to be done individually. Please feel free to consult
the professor, the T.A. or your fellow students for help with tools and
concepts. Please review the lab
requirements.
You are permitted to hand in code for this lab that contains
"magic numbers" and does not use generics.
Exercise (do not hand in)
Part 1: Finite State Machine Description
In this exercise, you will simulate behavioural VHDL code for a Mealy machine
that detects non-overlapping occurrences of the pattern "1101" and counts
up to at least 100 occurrences. Save the following two VHDL files
(shift+left_click).
pattern.vhd
count.vhd
Part 2: Design Entry
Login and create a directory "~/ee552/lab2".
% cd
% mkdir ee552
% mkdir ee552/lab2
Save the two VHDL files from your browser to this new directory and "cd"
to this directory.
Set this environment variable from the csh (note the single back-quotes,
usually above the tab key on the keyboard).
Invoke Design Architect:
Initialize a library called "work":
(toolbar) ModelSim => Lib...
In the text box, change the path so that it ends with "lab2/work". Press
Ok.
Now you are ready to load the VHDL design files:
(session pallet - right side) "open VHDL" icon
In the "VHDL Source Name" text box, append the file name "pattern.vhd"
to the path already shown. Press OK.
Repeat for the file "count.vhd".
Specify the library which your design will be compiled into (make sure
that the count7.vhd source code window is highlighted):
(toolbar) Compile => set options
Specify the library "work" in the current directory,
select VHDL 93, constraint checking and explicit scoping,
and for "additional vcom options", enter -93<space>.
Press OK.
Enter or modify the VHDL code for your design in the VHDL Editor window.
When finished, try to compile your count.vhd code. Select:
If you have errors, select the error message and click on Highlight
to show where the statement appears in your source code. The warning message
"Compilation canceled" can actually mean the compile succeeded without
errors.
Repeat the above for pattern.vhd (again specify the library "work")
and compile.
Part 3: Simulation
Click on the Design Architect background to deselect all windows. Invoke
the VHDL simulator:
(toolbar) ModelSim => Simulate...
Specify your library "work", units ns and click OK.
In the same dialog box, set the entity name to "pattern". ModelSim should
start and indicate that your design has been loaded.
From the ModelSim toolbar, bring up a list of signals
(ModelSim toolbar) View => Signals...
Now bring up the waveform display with all signals:
(Signals toolbar) View => Wave => Signals in design
Create some simulation stimuli. At the VSIM 3promt in the
ModelSim window, type:
force reset 1 0, 0 10
force clock 0 0, 1 5 -repeat 10
force bitstream 1 0, 0 50 -repeat 60
run
The force command takes a signal name, pairs of numbers describing an event
(level and time), and options. The first number in each pair is the
signal level and the second is the delay in ns after which the signal is
applied.
To test long bit patterns, it is easier to specify all of the
waveform stimulus into a command file such as the example that follows:
force reset 1 0, 0 10 -repeat 100
force clock 0 0, 1 5 -repeat 10
force bitstream 0 0, 0 10, 1 20, 0 30, 1 40, 0 50, 1 80
run 130
Save the above text into a file called "cmd.do".
Then from the ModelSim window, you can run this wave stimulus file using
the command
(toolbar) Macro->Execute Macro.
This will save you having to type in long sequences of force commands when
testing your circuit. Furthermore, to reset the simulation run so
that the time is at 0ns use the restart -f. Also, remember that if
you make changes to your VHDL code you have to recompile the design and
reload it using the menu option
(toolbar) File->Load New Design.
Click the run button to advance the simulation time further. Now, get a
printout:
(Wave toolbar) File => Print postscript...
You can also add stimuli to the simulation from the signals window.
This is useful for debugging individual architectures.
Try testing your system with the bit sequence "00010110001110111001101101011001011001100111"
or a sequence of your choosing.
Lab
Create a digital system using VHDL that detects the pattern "010" arriving
on either of two inputs (bitstream1, bitstream2). On each input,
detect non-overlapping patterns. Patterns, each of which arrive at
different inputs, should be detected, including two patterns arriving on
the two inputs out of phase.
Implement this system with Moore machines and a synchronous reset.
An example follows:
bitstream1 |
0 |
0 |
1 |
0 |
1 |
0 |
0 |
0 |
1 |
0 |
0 |
bitstream2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
match |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
1 |
1 |
You may use the following entity, or write your own:
entity pattern is
port (
reset, clock, bitstream1,
bitstream2: in std_ulogic;
match: out std_ulogic
);
end pattern;