------------------------------------------------- 
-- synchronous counter 
-- 
library ieee; 
use ieee.std_logic_1164.all; 
-- these packages allow math on std_logic
use ieee.std_logic_arith.all; 
use ieee.std_logic_unsigned.all; 

entity count is 
	generic ( counterwidth : positive := 7 );
    port(enable, aclr, clock : in std_logic; 
		q : buffer std_logic_vector(counterwidth-1
				downto 0)); -- buffer or not?
end count; 

architecture behaviour of count is 
begin 
counter :process(aclr, clock) 

    begin 
        if aclr = '1' then 
            q <= (others => '0'); 
		-- note not all synthesis tools like the two 
		-- conditionals following two lines combined
        elsif rising_edge(clock) then 
            if enable = '1' then 
                q <= q + '1';  
            end if; 
        end if; 
    end process counter; 

end behaviour;