EE 552 2003w 2003-1-17

Lab 2: VHDL for Synthesis

In this lab, you will write a behavioural description of a design in VHDL, suitable for synthesis.

Detailed directions for Mentor Graphics tools are given.  You will need to be able to use Mentor Graphics for later labs and the project.  Mentor Graphics also has a command line interface, which you are welcome to use.

This lab has two parts: an exercise that is not handed in, in which you will become familiar with the tools, and a lab that will be submitted for marking, in which you will create your own design.

Labs are to be done individually.  Please feel free to consult the professor, the T.A. or your fellow students for help with tools and concepts.  Please review the  lab requirements.

You are permitted to hand in code for this lab that contains "magic numbers" and does not use generics.
 

Exercise (do not hand in)

Part 1: Finite State Machine Description

In this exercise, you will simulate behavioural VHDL code for a Mealy machine that detects non-overlapping occurrences of the pattern "1101" and counts up to at least 100 occurrences.  Save the following two VHDL files (shift+left_click).

pattern.vhd
count.vhd

Part 2: Design Entry

Login and create a directory "~/ee552/lab2". Save the two VHDL files from your browser to this new directory and "cd" to this directory. Set this environment variable from the csh (note the  single back-quotes, usually above the tab key on the keyboard). Invoke Design Architect: Initialize a library called "work": In the text box, change the path so that it ends with "lab2/work". Press Ok.

Now you are ready to load the VHDL design files:

In the "VHDL Source Name" text box, append the file name "pattern.vhd" to the path already shown. Press OK.
Repeat for the file "count.vhd".

Specify the library which your design will be compiled into (make sure that the count.vhd source code window is highlighted):

Specify the library "work" in the current directory,
select VHDL 93, constraint checking and explicit scoping,
and for "additional vcom options", enter vcom -work work -93 -explicit counter.vhd
Press OK.
In subsequent runs for "additional vcom options", you may just enter -93<space>.
Enter or modify the VHDL code for your design in the VHDL Editor window.
When finished, try to compile your count.vhd code. Select: If you have errors, select the error message and click on Highlight to show where the statement appears in your source code. The warning message "Compilation canceled" can actually mean the compile succeeded without errors.

Click on the da background to deselect the vhdl editor window and repeat the above for pattern.vhd (again specify the library "work") and compile.
 

Part 3: Simulation

Click on the Design Architect background to deselect all windows. Invoke the VHDL simulator: Specify your library "work",  units ns and click OK. In the same dialog box, set the entity name to "pattern". ModelSim should start and indicate that your design has been loaded.
From the ModelSim toolbar, bring up a list of signals Now bring up the waveform display with all signals: Create some simulation stimuli.  At the VSIM prompt in the ModelSim window, type: The force command takes a signal name, pairs of numbers describing an event (level and time), and options.  The first number in each pair is the signal level and the second is the delay in ns after which the signal is applied.
 

To test long bit patterns, it is easier to specify all of the
waveform stimulus into a command file such as the example that follows:

force reset 1 0, 0 10 -repeat 100
force clock 0 0, 1 5 -repeat 10
force bitstream 0 0, 0 10, 1 20, 0 30, 1 40, 0 50, 1 80
run 130

Save the above text into a file called "cmd.do".

Then from the ModelSim window, you can run this wave stimulus file using the command

(toolbar) Macro->Execute Macro.
This will save you having to type in long sequences of force commands when testing your circuit.  Furthermore, to reset the simulation run so that the time is at 0ns use the restart -f.  Also, remember that if you make changes to your VHDL code you have to recompile the design and reload it using the menu option
(toolbar) File->Load New Design.
Click the run button to advance the simulation time further. Now, get a printout: You can also add stimuli to the simulation from the signals window.  This is useful for debugging individual architectures.

Try testing your system with the bit sequence "00010110001110111001101101011001011001100111" or a sequence of your choosing.
 

Command line interface

Alternatively, these tools can be operated with the command line interface (Parts 1, 2, and the first bit of 3):

cd ee552
mkdir lab2
cd lab2
setenv MGC_WD `pwd`
wget http://www.ee.ualberta.ca/~elliott/ee552/labs/pattern.vhd
wget http://www.ee.ualberta.ca/~elliott/ee552/labs/count.vhd
vlib work
vcom -work work -explicit -93 count.vhd
vcom -work work -explicit -93 pattern.vhd
vsim -lib work -i -t ns work.pattern
 
 
 

Lab

You have been asked to design a circuit that converts a serial bit stream (data_in) into an 8-bit wide parallel signal (data_out).  The least significant bit, bit-0, arrives first, indicated by a high level on the signal, first_bit (always seen every 8 clock cycles).  When new data is placed on the output, data_out_valid should be raised for one clock cycle.  Use the rising edge of the clock.  Write commented synthesizable RTL VHDL code for this circuit. Try to keep the implementation (code and synthesized hardware complexity) as small as possible.  You may be surprised how short the solution can be.