Computer Architecture Discussion Group Schedule

All are invited to attend the whole series, or just the papers that catch your imagination.  I expect regular attendees to also act as discussion leader.  This discussion group is held in conjunction with EE602 Computer Architecture.
http://www.ee.ualberta.ca/~elliott/ee602/

Discussion leaders will make an informal 30 minute presentation of the main work in a paper, including a critique.  Finally, everyone will jump in with their thoughts on the paper.  Leaders can pick a paper on Computer Architecture from my list or search for their own favourite.

People are also welcome to use this forum to get feedback on their presentations prior to conferences.

Please let me know if you'ld like to be added to the mailing list or schedule a slot as discussion leader.
 
 

View the directory of all papers.

Abstracts

Burns, R. C., R. M. Rees, and D. D. E. Long.
Safe Caching in a Distributed File System

In Proceedings of the International Parallel and Distributed Processing Symposium. Cancun, Mexico, May, 2000.
http://www.cse.ucsc.edu/~randal/pubs.html

In a distributed file system built on network attached storage, client computers access data directly from shared storage, rather than submitting I/O requests through a server. Without a server marshaling access to data, if a computer fails or becomes isolated in a network partition while holding locks on cached data objects, those objects become inaccessible to other computers until a locking authority can guarantee that the lock holder will not again directly access these data. We describe a server that acts as the locking authority and implements a lease-based protocol for revoking access to data objects locked by an isolated or failed computer. When a
lease expires, the server can be assured that the client no longer acts on locked data, and can safely redistribute locks to other clients.  During normal operation, this protocol invokes no message overhead, and uses no memory and performs no computation at the locking authority.
 
 

Craig Joly

SIMULTANEOUS MULTITHREADING: A Platform for Next-Generation Processors

Susan J. Eggers University of Washington
Joel S. Emer Digital Equipment Corp.
Henry M. Levy University of Washington
Jack L. Lo University of Washington
Rebecca L. Stamm Digital Equipment Corp.
Dean M. Tullsen University of California, San Diego

Simultaneous multithreading exploits both instruction-level and thread-level parallelism by issuing instructions from different threads in the same cycle.

As the processor community prepares for a billion transistors on a chip, researchers continue to debate the most effective way to use them. One approach is to add more memory (either cache or primary memory) to the chip, but the performance gain from memory alone is limited. Another approach is to increase the level of systems integration, bringing sup-port functions like graphics accelerators and I/O controllers on chip. Although integra-tion lowers system costs and communica-tion latency, the overall performance gain to applications is again marginal.
 
 
 
 

Duncan Elliott

INTRODUCING THE IA-64 ARCHITECTURE

ADVANCES IN MICROPROCESSOR DESIGN, INTEGRATED CIRCUITS, AND COMPILER TECHNOLOGY HAVE INCREASED THE INTEREST IN PARALLEL INSTRUCTION EXECUTION. A JOINT HP-INTEL TEAM DESIGNED THE IA-64 PROCESSOR INSTRUCTION SET ARCHITECTURE WITH PARALLELISM IN MIND.

with references to:
ITANIUM PROCESSOR MICROARCHITECTURE

THE ITANIUM PROCESSOR EMPLOYS THE EPIC DESIGN STYLE TO EXPLOIT INSTRUCTION-LEVEL PARALLELISM. ITS HARDWARE AND SOFTWARE WORK IN CONCERT TO DELIVER HIGHER PERFORMANCE THROUGH A SIMPLER, MORE EFFICIENT DESIGN.