ECE511 Digital ASIC Design

ECE511 Digital ASIC Design, Fall 2021

Instructor

Dr. Jie Han, office: 13-358, D-ICE Building, phone: 492-1361

Email: jhan8 (and you should know what follows), homepage

Office Hours: Friday, 3:00 - 4:00pm, or by appointments.

Course Information

Lectures: Monday and Wednesday, 3:00 - 4:20 PM

Room: Hybrid in ECERF W6-087 via Zoom in eClass

Website: eClass @ the University (Enrolled students will be able to access it by logging into the eClass@UofA.)

Lab information is available in eClass.

Prerequisite

Restricted to graduate students, or consent of the Department.

Course Description

ECE 511 discusses advanced integrated circuit design using the hardware description language VHDL, with a focus on larger scale digital systems. Students will design and implement a digital system using field-programmable gate arrays (FPGAs) as a course project.

Course Objectives

At the end of the course, the student will be able to design digital systems including arithmetic circuits using VHDL and FPGAs, and understand the current trends in some research areas of digital circuits and systems.

Course Outline:

1. Review of integrated circuit technology and evolution of FPGA technology. (1 week approx.)

2. VHDL hardware description language and design methodology at the gate and register transfer levels. (3 weeks approx.)

3. Digital system and finite state machine (FSM) design. (2 weeks approx.)

4. Design of arithmetic circuits: adders, multipliers, and dividers, among others. (3 weeks approx.)

5. Approximate and stochastic computing, fault tolerance and neural networks. (2 weeks approx.)

Advanced topics covered by student presentations. (2 weeks approx.)

Textbooks

Peter J. Ashenden: The Designer's Guide to VHDL, 3rd edition, Morgan Kaufmann Publishers, 2008, ISBN 978-0-12-088785-9. This book provides a broad and thorough survey of the full version of VHDL as a hardware specification and description language.

Mark Zwolinski: Digital System Design with VHDL, 2nd edition, Prentice Hall, 2004, ISBN 0-13-039985-X. This book covers the methodology of digital system design using VHDL.

And complementary lecture notes/slides.

Marking scheme:

Assignments: 5%

Laboratory: 15% (See eClass for detail)

Midterm Exam: 15% (Tentatively scheduled on October 27, Wednesday)

Presentation: 10% (A 10-15 min project presentation in the last two weeks of the class)

Project Report: 30% (A formal report for the project, due at the end of the term)

Final Exam: 25% (See Beartracks)

Academic integrity

The University of Alberta is committed to the highest standards of academic integrity and honesty. Students are expected to be familiar with these standards regarding academic honesty and to uphold the policies of the University in this respect. Students are particularly urged to familiarize themselves with the provisions of the Code of Student Behavior (online at www.governance.ualberta.ca ) and avoid any behavior which could potentially result in suspicions of cheating, plagiarism, misrepresentation of facts and/or participation in an offense. Academic dishonesty is a serious offense and can result in suspension or expulsion from the University.

Recording is permitted only with the prior written consent of the professor or if recording is part of an approved accommodation plan.

Policy about course outlines can be found in §23.4(2) of the University Calendar.