ECE 410 Advanced Digital Logic Design

ECE 410 (CMPE 480) Advanced Digital Logic Design, Fall 2014

Instructor

Dr. Jie Han, office: W2-079, ECERF, phone: 492-1361

Email: jhan8 (and you know what follows), homepage

Office Hours: Friday, 2:00 - 3:00pm, or by appointments.

Lab Instructor

Zhixi Yang (Email: zhixi) and Mahdi Karami (Email: karami1)

Teaching Assistants

Peican Zhu

Fatema Liza

Course Information

Lectures: Tuesday and Thursday, 12:30 - 1:50pm

Room: BS G116

Website: eClass @ the University (Enrolled students will be able to access it by logging into the eClass@UofA.)

A separate eClass page has been created for the labs.

Prerequisite

EE280 Introduction to Digital Logic Design, or consent of the Department.

Course Description

ECE 410 covers modern digital system design methodology using the hardware description language VHDL and synthesis tools that automatically simplify and map digital system designs to field-programmable gate array (FPGA) configurable hardware.

Course Objectives

At the end of the course, the student will be able to design combinational and sequential circuits using VHDL, use tools to synthesize and map designs onto FPGAs, carry out arithmetic circuit design and understand the fundamentals of digital system testing.

Course Outline:

1. Review of classical sequential logic design. (1 week approx.)

2. VHDL hardware description language and logic simulation. (3 weeks approx.)

3. Digital system design. (4 weeks approx.)

4. Design of arithmetic circuits. (3 weeks approx.)

Introduction to digital system testing. (1 week approx.)

Textbooks

Peter J. Ashenden, The Designer's Guide to VHDL, 3rd edition, Morgan Kaufmann Publishers, 2008, ISBN 978-0-12-088785-9. This book provides a broad and thorough survey of the full version of VHDL as a hardware specification and description language. It covers new features introduced in the 2008 updated version of VHDL. There is less coverage, however, of design methodology and on synthesizeable subsets of VHDL. This last material will be covered in the lectures.

Mark Zwolinski, Digital System Design with VHDL, 2nd edition, Prentice Hall, 2004, ISBN 0-13-039985-X. This book covers the methodology of digital system design using VHDL. The first part of lecture notes in the course follows this book fairly closely.

Frank Vahid, Digital Design (with RTL Design, VHDL, and Verilog), 2nd edition, John Wiley and Sons Publishers, 2011. This book contains many interesting examples, some of which are covered in the lectures.

And more than 500 slides.

Marking scheme:

Assignments: 10% (Approximately six times)

Laboratory: 20% (Four lab sections: see eClass lab page for detail)

Midterm Exam: 25% (Tentatively scheduled in the last week of October)

Final Exam: 45% (Tentative date: 11-Dec-2014 (Thursday) @ 2:00 p.m.)

Academic integrity

The University of Alberta is committed to the highest standards of academic integrity and honesty. Students are expected to be familiar with these standards regarding academic honesty and to uphold the policies of the University in this respect. Students are particularly urged to familiarize themselves with the provisions of the Code of Student Behavior (online at www.governance.ualberta.ca ) and avoid any behavior which could potentially result in suspicions of cheating, plagiarism, misrepresentation of facts and/or participation in an offense. Academic dishonesty is a serious offense and can result in suspension or expulsion from the University.

“Recording is permitted only with the prior written consent of the professor or if recording is part of an approved accommodation plan.”

Policy about course outlines can be found in §23.4(2) of the University Calendar.