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- Near Future Research Projects
The NEWAGE project is an ambitious large-scale network environment emulation system consisting of a multitude of specialized FPGA and compute blades interconnected in a server environment which allows the sample-signal-accurate emulation of transmission, the channel, and the receiver systems, which are controlled by realistic data traffic generated by compute servers. In this way, complex wireless networks can be emulated “in vitro” without the costly prototype deployments otherwise required. NEWAGE is an ambitious and advanced concept to allow researchers and industrial partners alike to test specific networking, signaling, or communications methods, circuit cores, or algorithms, to be tested in accurately represented, but artificial transmission environments. To enable this, hundreds of complex transmission channels will need to be accurately emulated and coordinated. This requires a complex state-of-the art specialized compute environment. The different components of such a set-up are currently being investigated, and a small demonstration set-up is targeted to come on-line this fall.
Multiple Access Communications
In the area of multiple access communications we have identified a winning signaling strategy with our invention of partitioned signaling. Future research will concentrate on integrating this concept into efficient networking and relaying research. We will also study various implementation aspects of partitioned signaling, in particular the required auxiliary functions of timing and phase synchronization. The concepts of partitioned signaling need to be studied in view of efficient low-complexity implementations, which then need to be verified by simulation, and prototyping on NEWAGE.
Networking research will play an important role in future extensions. As wireless packet networking becomes ever more important, the management and efficient routing of datagrams, or communications packets, becomes a central concern. Primarily, we plan to expand our activities to include efficient routing at the higher network layers, with cognizance of advanced signal processing capabilities of the physical layer. We plan on integrating advanced joint detection methodologies, primarily and initially our proposed random-packet CDMA, into higher networking studies. Ad hoc networking research is also a new direction we are expanding, primarily the study and applicability of advanced signal processing methods such as joint detection, cooperative distributed antenna arrays, and adequate synchronization methods and detection methods, as well as the impact of traffic and traffic coordination on network capacity. Primarily, each link in such a network has to be made highly reliable, or accumulated packet loss will further degrade an already modest inherent network capacity. Our concept of partitioned signaling should be very useful in this environment, as it allows for essentially arbitrary traffic levels at the cost of access power.
Error Control Coding, Low-Power Circuits
Our work in error control coding and low-power circuits enters a new phase with an emphasis on power-efficient processing. This requires the judicious combination of both theoretical tools and ideas, such as our low-power message formats and density evolution analysis for LDPC codes, as well as the design of ultra-low power circuits to execute the required functions of our algorithms. This effort involves the tight collaboration between VLSI researchers and algorithmic signal processing researchers, a combination ideally afforded by the interdisciplinary character of the HCDC. Power will play a key role in all future digital signal processing, from communications systems to computational devices (microprocessors). Our efforts will combine algorithmic and circuit design research to deliver the lowest power solutions to a given communications problem
The projects on analog decoding also refocus on energy efficiency. The question is where and how analog processing should and can replace traditional digital computation to provide more power-efficient solutions. There is ample demonstration that analog decoding can provide energy efficient error control decoding solutions using main-stream CMOS process technology at 180nm and 130nm. Beyond this, the scaling of analog technology remains an active research area. Analog processing has also been recognized for its power-efficiency potential in standard filtering applications, where analog circuit solutions provide significantly superior solutions. We continue to research this topic, primarily scaling issues and the question on how to combine conventional analog processing with the analog information processing methodology pioneered by HCDC in order to build advanced iterative receiver systems with minimal processing power requirements. Collaboration with ENST Bretagne has been initiated on the design of analog decoders in state-of-the-art 65-nm CMOS technologies. Transistors in these new technologies exhibit different characteristics from those in more mature technologies.
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