EE 340 - Electronic Devices

Lec A1 Home Page - Fall 2009

1. General Information

 

Instructor

 

Prof. Stephane Evoy

Room ECERF W2-114

Phone: 492-5866

Email: evoy@ece.ualberta.ca

Office hours: Mon 1-3 p, Tue 9:30-10:30 Wed 1-3 p,

 

Class Information

 

Lectures: MWF 10:00-10:50, ETLC 2-002

Seminars: Thu  1:00 - 1:50, NRE 1 001

Teaching Assistant

 

TBA

 

 

 

2. Course Objectives

:

·         Identify active device circuit elements, their terminals, and connections

·         Outline and execute procedures for analysing diode, transistor, and amplifier circuits

·         Explain the physical operation of the electronic devices studied in this course using basic (classical) physical electronic concepts and terminology

·         Distinguish between DC and AC signals and between large- and small-signal analysis regimes

·         Interpret the current-voltage characteristics of electronic devices

·         Apply small-signal circuit models to electonic circuits

·         Identify mode of operation of electronic devices, apply appropriate models and equations to analyse circuits built on said devices

·         Calculate voltages or currents in small-signal circuit analysis

·         Derive expressions linking voltages/currents and device parameters of diodes/transistors

·         Evaluate and optimise the performance of electronic circuits (both models and lab designs)

·         Design (in the lab) electronic circuits to meet the design objectives, implement a prototype of the design, test its operation (measurements), verify the design using circuit simulation, and evaluate the design (report)

 

3. Required Text

 

Microelectronic Circuits (5th edition)

Authors: Adel S. Sedra, Kenneth C. Smith, K.C. Smith, Kenneth Carless Smith

Format: Hardcover, 1360 pages

Publisher: Oxford Univ Pr

ISBN-10: 0195142519

ISBN-13: 9780195142518

Text Website

4. Approximate Lecture Timeline

 

Weeks

Broad Topic

Concepts

1-2

Basics of diodes

Diode models, Breakdown and Zener diodes, circuit applications of diodes.

2-3

Semiconductor physics and p-n junctions

Semiconductors, electrons and holes, doping of semiconductors, drift and diffusion, the p-n junction, another look at the diode models

4-7

Bipolar junction transistors (BJTs)

Basic structure and physics, modes of operation, npn and pnp transistors, i-v characteristics, BJT as an amplifier and as a switch, small and large signal models

8-10

Field effect transistors (FETs)

Enhancement- and depletion-type MOSFETs, basic structure and physics, i-v characteristics, FET as an amplifier and as a switch, digital logic based on FETs, integrated circuits

11-12

Differential amplifiers

FET differential pair, differential amplifiers with active loads

 

 

5. Lecture Timetable (Tentative)

 

Lecture

Main Concepts

Sections in Sedra and Smith

1

Ideal diodes and analysis of diode circuits

3.1

2

Ideal diodes and the forward characteristics of real diodes

3.2 to 3.3

3

Diode reverse breakdown characteristics, Zener diodes

3.4

4

Diode rectifier circuits and application to DC power supplies

3.5 and 3.9

5

Basic semiconductor concepts – electrons and holes, energy gap, electron-hole-pair generation

3.7.1

6

Holes, recombination, intrinsic carrier concentration

3.7.1

7

Conduction in semiconductors – drift and diffusion

3.7.1

8

Doped semiconductors, the mass-action law

3.7.1

9

The open-circuit pn junction

3.7.2

10

The reverse-biased pn junction, depletion capacitance, breakdown in the pn junction

3.7.3-3.7.4

11

The forward-biased pn junction

3.7.5

12

Diode ideality factor, relationship between bandgap and cut-in voltage, short diodes, diffusion capacitance, dynamic diode resistance

3.7.5, 3.3.8

13

Linearity and superposition review, diode small signal model

3.3.8

14

Introduction to the BJT, forward active mode of the BJT

5.1.1-5.1.2

15

Forward active mode current relationships, beta and alpha, large signal models for the forward active mode

5.1.2

16

Reverse active mode, Ebers-Moll (EM) model, saturation mode

5.1.3-5.1.5

17

BJT circuit symbols, graphical representations of transistor characteristics, the Early effect

5.2.1-5.2.2

18

Large- and small-signal common emitter current gain, BJT data sheets, BJT breakdown, the Early effect in common-emitter characteristics

5.2.3-5.2.4

19

Common-emitter amplifier, skeleton circuit and basic concepts

5.3.1-5.3.2

20

Graphical analysis of common emitter amplifier, classical biasing arrangmenet for BJT amplifiers

5.3.3, 5.5.1

21

Biasing of BJT amps, small signal model for BJT

5.5.2-5.5.4, 5.6

22

Single-stage BJT amplifiers

5.7

23

Common emitter amp, common base amp, voltage buffer amps

5.7, 1.5, 2.3.4

24

Common collector amp, summary of BJT amps

5.7

25

MOSFET introduction, n-channel enhancement MOSFET

4.1.1-4.1.5

26

MOSFET i-v characteristics and large signal model

4.1.6, 4.2.1-2

27

Channel length modulation, p-channel enhancement MOSFET, CMOS, MOSFET as an amplifier and switch

4.2.3-4, 4.1.7-8, 4.3, 4.4.1-3

28

MOSFET as an amplifier, biasing MOSFET amplifier circuits

4.4.5-6, 4.5

29

MOSFET small signal models, single-stage MOSFET amps

4.6, 4.7.1

30

Digital logic inverters, CMOS digital logic inverter

1.7.1-5, 4.10

31

Difference amplifiers, MOS differential pair amp large signal properties

2.4, 7.1

32

Small signal analysis of MOSFET diff pair amp, non-idealities

7.2

 

6. Grading

 

Item

Weight

Date

Problem sets

10%

 

Design lab:

15%

 

Examination #1:

25%

TBA

Examination #2:

25%

TBA

Examination #3:

25%

TBA

Total:

100%

 

 

 

7. Other Policies

 

·       Problem sets and their solutions will be distributed by email

 

·       The content of the three examinations is *not* cumulative

 

·       Homework assignments are expected to be independent work. Plagiarism and/or “carbon copies”will not be tolerated, will result in a grade of zero for that HW, and will be reported to School authorities

 

·        Lateness penalty for homework:  30 % off of score (at 4:01 pp) + 0.3 % per additional hour (nights and week-ends included).

 

·        Lateness due to sickness or other major issues should be noted to Dr. Evoy by email prior to the HW deadline. Medical or other signed note will then be expected afterwards.