-- EE 552 Project
-- Dustin Demontigny
-- March 21, 2003
-- reg_control.vhd
-- control the data flow to and from registers

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

use work.smart_eq_pack.all;

entity reg_control is
	port(clock, reset : in std_logic;
			new_gain, send_coefs : in std_logic;
			new_coefs, send_gain : out std_logic;
			load_gain, shift_gain : out std_logic;
			clock_accum, clr_accum : out std_logic;
			load_coef, shift_coefs : out std_logic);
end reg_control;

architecture mixed of reg_control is
	type state_type is (load, accum, shift, next_coef, pause);
	signal state: state_type ;  
begin
	contol : process (clock,reset)
		variable bandcount : natural range 0 to bands;
		variable tapcount : natural range 0 to taps;
	begin
     if (reset ='0') then
       state <= load; 
     elsif (clock = '1' and clock'event) then       
			case state is
				when load =>
					new_coefs <= '1';                  
					load_gain <= '1';
					clr_accum <= '0';
					state <= accum;
         when accum =>
					new_coefs <= '0';
					shift_coefs <= '0';
					clock_accum <= '1';
					shift_gain <= '0'; 
					load_gain <= '0';
					clr_accum <= '0';
					state <= shift;
				when shift =>
					clock_accum <= '0';
					shift_gain <= '1';
					bandcount := bandcount + 1;
					if bandcount = bands then
						bandcount := 0;
						load_coef <= '1';
						state <= next_coef;
					else 
						state <= accum;
					end if;
				when next_coef =>
					tapcount := tapcount + 1;
					load_coef <= '0';
					shift_coefs <= '1';
					state <= pause;
				when pause =>
					clr_accum <= '1';
					shift_coefs <= '0';
					if tapcount = taps then
						tapcount := 0;
						--coefs are ready here
						state <= load;
					else
						state <= accum;
					end if;
				when others => 
					state <= load;
			end case;
		end if; 
	end process;
end mixed;