FPGA Resource Optimization

EE 552 Winter 2003 - Smart Equalizer Project

Group Members: Dustin Demontigny - demontig@ee.ualberta.ca, Dave Bull - bull@ee.ualberta.ca

Written By: Dustin Demontigny

Introduction: The resource requirements of an FPGA system is dependent on the manner in which the HDL source code is written. Software optimization tools, although very useful, often lead to unpredictable results. Two very similar versions of an HDL file can be implemented much differently. Sometimes the same file will be synthesized differently in a different context. This application note outlines a very simple modification to VHDL code that will greatly reduce the resource requirements of the FPGA.

NOTE: The Smart Equalizer Project uses the XSA-100 and Xstend boards. The VHDL code was compiled, synthesized and implemented using Model Sim XE 5.5e and Xilinx Project Navigator 4.2i. Other systems might produce slightly different results.

Description: Integer variables are often used as counters or flags in process statements. The implementation of these integers is strongly dependent on the manner in which they are declared. If the integer is unbounded or not given a range, the space required on the FPGA can be large. The following declares an unbounded integer variable:

variable flag : integer := 0;

The variables used in a process are often restricted to a certain range. In the case of a flag, the range would be between 0 and 1. To reduce the FPGA space required to implement a variable, limit the integer's value to a certain range during declaration. This is shown in the following:

variable flag : natural range 0 to 1;

The reserved word natural is used to describe an integer greater than or equal to zero. This extremely simple change requires the programmer to specify the range of the integer which isn't always possible. In most cases however, this works very well.

Example: Some files that used this optimization procedure are located in the parent directory. For instance, debouncer3.vhd uses a variable count on line 25 to debounce the input pushbuttons. Originally the variable was declared as follows:

variable count : integer := 0;

When implemented, this entity uses 42 slices and 5% of the FPGA. To reduce the space and size, line 25 was changed to the following:

variable count : natural range 0 to debounce_delay;

The constant debounce_delay is declared in the project's top level package file. It determines the amount of clock cycles to delay before mapping the inputs to the outputs. The amount of slices is not greatly affected by the value of the debounce_delay (for values from 1 to 1023). By using a bound integer, the size of the debouncer reduces to 12 slices and 1% of the FPGA. The following table summarizes the FPGA resources requirements for certain VHDL files used in the Smart Equalizer project before and after this optimization technique.

For the User Interface and Arithmetic Unit used, this optimization technique saved 185 slices, which is roughly half of the 374 slices required prior to using bound integers.

Group Members: Dustin Demontigny - demontig@ee.ualberta. ca, Dave Bull - bull@ee.ualberta.ca