LIBRARY IEEE,work;
USE IEEE.std_logic_1164.ALL;
USE IEEE.std_logic_unsigned.ALL;
USE work.codec.ALL;

ENTITY codec_intfc IS
GENERIC
(
DAC_WIDTH: positive := 20;
ADC_WIDTH: positive := 20;
CHANNEL_DURATION: positive := 128 -- must be 128
);
PORT
(
-- interface I/O signals
clk: IN std_logic; -- clock input
reset: IN std_logic; -- synchronous active-high reset
lrsel: IN std_logic; -- select L/R channel for read/write
rd: IN std_logic; -- read from the codec ADC
wr: IN std_logic; -- write to the codec DAC
ladc_out: OUT std_logic_vector(ADC_WIDTH-1 DOWNTO 0); -- L ADC
radc_out: OUT std_logic_vector(ADC_WIDTH-1 DOWNTO 0); -- R ADC
ldac_in: IN std_logic_vector(DAC_WIDTH-1 DOWNTO 0); -- left DAC
rdac_in: IN std_logic_vector(DAC_WIDTH-1 DOWNTO 0); -- right DAC
ladc_out_rdy: OUT std_logic; -- left ADC output ready to read
radc_out_rdy: OUT std_logic; -- right ADC output ready to read
adc_overrun: OUT std_logic; -- ADC overwritten before read
ldac_in_rdy: OUT std_logic; -- left DAC in ready to be written
rdac_in_rdy: OUT std_logic; --right DAC in ready to be written
dac_underrun: OUT std_logic; -- DAC did not receive data in time
-- codec chip I/O signals
mclk: OUT std_logic; -- master clock output to codec
sclk: OUT std_logic; -- serial data clock to codec
lrck: OUT std_logic; -- left/right codec channel select
sdin: OUT std_logic; -- serial output to codec DAC
sdout: IN std_logic -- serial input from codec ADC
);
END codec_intfc;

ARCHITECTURE codec_intfc_arch OF codec_intfc IS
SIGNAL mclk_int: std_logic; -- internal codec master clock
SIGNAL lrck_int: std_logic; -- internal L/R codec channel select
SIGNAL sclk_int: std_logic; -- internal codec data shift clock
SIGNAL bit_cntr: std_logic_vector(5 DOWNTO 0);
SIGNAL subcycle_cntr: std_logic_vector(1 DOWNTO 0);
SIGNAL lsdin: std_logic;
SIGNAL rsdin: std_logic;
SIGNAL ladc_overrun: std_logic;
SIGNAL radc_overrun: std_logic;
SIGNAL ldac_underrun: std_logic;
SIGNAL rdac_underrun: std_logic;
SIGNAL lchan_sel: std_logic;
SIGNAL rchan_sel: std_logic;
SIGNAL lchan_on: std_logic;
SIGNAL rchan_on: std_logic;
SIGNAL feeder: std_logic_vector(DAC_WIDTH-1 downto 0);-- added by ME****
BEGIN

u0: clkgen
GENERIC MAP
(
CHANNEL_DURATION=>CHANNEL_DURATION
)
PORT MAP
(
clk=>clk,
reset=>reset,
mclk=>mclk_int,
sclk=>sclk_int,
lrck=>lrck_int,
bit_cntr=>bit_cntr,
subcycle_cntr=>subcycle_cntr
);
lrck <= NOT(lrck_int); -- invert for inverter in XStend V1.3
mclk <= NOT(mclk_int);
sclk <= NOT(sclk_int);

lchan_sel <= YES WHEN lrsel=LEFT ELSE NO;
lchan_on <= YES WHEN lrck_int=LEFT ELSE NO;
u_left: channel
GENERIC MAP
(
DAC_WIDTH=>DAC_WIDTH,
ADC_WIDTH=>ADC_WIDTH
)
PORT MAP
(
clk=>clk,
reset=>reset,
chan_on=>lchan_on,
bit_cntr=>bit_cntr,
subcycle_cntr=>subcycle_cntr,
chan_sel=>lchan_sel,
rd=>rd,
wr=>wr,
adc_out=>ladc_out,
dac_in=>ldac_in,
adc_out_rdy=>ladc_out_rdy,
adc_overrun=>ladc_overrun,
dac_in_rdy=>ldac_in_rdy,
dac_underrun=>ldac_underrun,
sdin=>lsdin,
sdout=>sdout
);

rchan_sel <= YES WHEN lrsel=RIGHT ELSE NO;
rchan_on <= YES WHEN lrck_int=RIGHT ELSE NO;
u_right: channel
GENERIC MAP
(
DAC_WIDTH=>DAC_WIDTH,
ADC_WIDTH=>ADC_WIDTH
)
PORT MAP
(
clk=>clk,
reset=>reset,
chan_on=>rchan_on,
bit_cntr=>bit_cntr,
subcycle_cntr=>subcycle_cntr,
chan_sel=>rchan_sel,
rd=>rd,
wr=>wr,
adc_out=>radc_out,
dac_in=>rdac_in,
adc_out_rdy=>radc_out_rdy,
adc_overrun=>radc_overrun,
dac_in_rdy=>rdac_in_rdy,
dac_underrun=>rdac_underrun,
sdin=>rsdin,
sdout=>sdout
);
dac_underrun <= YES WHEN ldac_underrun=YES OR rdac_underrun=YES
ELSE NO;
adc_overrun <= YES WHEN ladc_overrun=YES OR radc_overrun=YES
ELSE NO;

-- generates the serial data output to the SDIN pin of the
-- codec DAC depending on which channel is being loaded
sdin <= NOT(lsdin) WHEN lrck_int=LEFT ELSE NOT(rsdin);

END codec_intfc_arch;