LIBRARY IEEE,work;
USE IEEE.std_logic_1164.ALL;
USE IEEE.std_logic_unsigned.ALL;
USE work.codec.ALL;
ENTITY channel IS
GENERIC
(
DAC_WIDTH: positive := 20;
ADC_WIDTH: positive := 20
);
PORT
(
-- interface I/O signals
clk: IN std_logic; -- clock input
reset: IN std_logic; -- synchronous active-high reset
chan_on: IN std_logic;
bit_cntr: IN std_logic_vector(5 DOWNTO 0);
subcycle_cntr: IN std_logic_vector(1 DOWNTO 0);
chan_sel: IN std_logic; -- select L/R channel for read/write
rd: IN std_logic; -- read from the codec ADC
wr: IN std_logic; -- write to the codec DAC
adc_out: OUT std_logic_vector(ADC_WIDTH-1 DOWNTO 0); -- ADC output
dac_in: IN std_logic_vector(DAC_WIDTH-1 DOWNTO 0); -- DAC input
adc_out_rdy: OUT std_logic; -- ADC output is ready to be read
adc_overrun: OUT std_logic; -- ADC overwritten before being read
dac_in_rdy: OUT std_logic; -- DAC input is ready to be written
dac_underrun: OUT std_logic; -- input to DAC arrived late
-- codec chip I/O signals
sdin: OUT std_logic; -- serial output to codec DAC
sdout: IN std_logic -- serial input from codec ADC
);
END channel;

ARCHITECTURE channel_arch OF channel IS
SIGNAL dac_shfreg: std_logic_vector(DAC_WIDTH-1 DOWNTO 0);
SIGNAL dac_empty: std_logic; -- DAC shift register is empty
SIGNAL dac_wr: std_logic; -- the DAC channel has been written
SIGNAL dac_wr_nxt: std_logic; -- the DAC channel has been written
SIGNAL dac_in_rdy_int: std_logic; -- internal version of dac_in_rdy
SIGNAL adc_shfreg: std_logic_vector(ADC_WIDTH-1 DOWNTO 0);
SIGNAL adc_full: std_logic; -- ADC shift register is full
SIGNAL adc_rd: std_logic; -- the ADC channel has been read
SIGNAL adc_rd_nxt: std_logic; -- the ADC channel has been read
SIGNAL adc_out_rdy_int: std_logic; -- internal version adc_out_rdy
BEGIN
-- receives data from codec ADC
rcv_adc:
PROCESS(clk,chan_on,subcycle_cntr,bit_cntr,adc_shfreg,sdout)
BEGIN
IF(clk'event AND (clk=YES)) THEN
IF(reset='1') THEN
adc_shfreg <= (OTHERS=>'0');
adc_full <= NO;
ELSIF((chan_on=YES) AND (subcycle_cntr=2)) THEN
IF(bit_cntr<ADC_WIDTH-1) THEN
adc_full <= NO;
adc_shfreg <= adc_shfreg(ADC_WIDTH-2 DOWNTO 0) & sdout;
ELSIF(bit_cntr=ADC_WIDTH-1) THEN
adc_full <= YES;
adc_shfreg <= adc_shfreg(ADC_WIDTH-2 DOWNTO 0) & sdout;
END IF;
END IF;
END IF;
END PROCESS;
adc_out <= adc_shfreg;
-- handle reading of ADC data from codec interface
adc_rd_nxt <= YES WHEN (adc_full=YES AND chan_sel=YES AND rd=YES) OR
(adc_full=YES AND adc_rd=YES)
ELSE NO;
read_adc:
PROCESS(clk,adc_rd_nxt)
BEGIN
IF(clk'event AND clk='1') THEN
IF(reset=YES) THEN
adc_rd <= NO;
ELSE
adc_rd <= adc_rd_nxt;
END IF;
END IF;
END PROCESS;
-- ADC data is ready if register is full and hasn't been read yet
adc_out_rdy_int <= YES WHEN adc_full=YES AND adc_rd=NO ELSE NO;
adc_out_rdy <= adc_out_rdy_int;

-- detect and signal overwriting of data from the codec ADC channels
detect_adc_overrun:
PROCESS(clk,reset,bit_cntr,chan_on,adc_out_rdy_int)
BEGIN
IF(clk'event AND clk='1') THEN
IF(reset=YES) THEN
adc_overrun <= NO;
ELSIF(bit_cntr=1 AND chan_on=YES AND adc_out_rdy_int=YES) THEN
adc_overrun <= YES;
END IF;
END IF;
END PROCESS;

-- transmits data to codec DAC
tx_dac:
PROCESS(clk,reset,chan_on,subcycle_cntr,bit_cntr,dac_shfreg)
BEGIN
IF(clk'event AND clk='1') THEN
IF(reset=YES) THEN
dac_shfreg <= (OTHERS=>'0');
dac_empty <= YES;
ELSIF(chan_sel=YES AND wr=YES) THEN
dac_shfreg <= dac_in;
ELSIF(chan_on=YES AND subcycle_cntr=2) THEN
IF(bit_cntr<DAC_WIDTH-1) THEN
dac_empty <= NO;
dac_shfreg <= dac_shfreg(DAC_WIDTH-2 DOWNTO 0) & '0';
ELSIF(bit_cntr=DAC_WIDTH-1) THEN
dac_empty <= YES;
dac_shfreg <= dac_shfreg(DAC_WIDTH-2 DOWNTO 0) & '0';
END IF;
END IF;
END IF;
END PROCESS;

-- output the serial data to the SDIN pin of the codec DAC
sdin <= dac_shfreg(DAC_WIDTH-1) WHEN chan_on=YES ELSE '0';

-- handle writing of DAC data from codec interface
dac_wr_nxt <= YES WHEN (dac_empty=YES AND chan_sel=YES AND wr=YES) OR
(dac_empty=YES AND dac_wr=YES)
ELSE NO;
write_dac:
PROCESS(clk,reset,dac_wr_nxt)
BEGIN
IF(clk'event AND clk='1') THEN
IF(reset=YES) THEN
dac_wr <= NO;
ELSE
dac_wr <= dac_wr_nxt;
END IF;
END IF;
END PROCESS;
-- DAC is ready if register is empty and hasn't been written yet
dac_in_rdy_int <= YES WHEN dac_empty=YES AND dac_wr=NO ELSE NO;
dac_in_rdy <= dac_in_rdy_int;

-- detect and signal underflow of data to the codec DAC channels
detect_dac_underrun:
PROCESS(clk,reset,bit_cntr,chan_on,dac_in_rdy_int)
BEGIN
IF(clk'event AND clk='1') THEN
IF(reset=YES) THEN
dac_underrun <= NO;
ELSIF(bit_cntr=1 AND chan_on=YES AND dac_in_rdy_int=YES) THEN
dac_underrun <= YES;
END IF;
END IF;
END PROCESS;
END channel_arch;