SDRAM Controller

This app notes provides documentation on the SDRAM controller originally developed by Altera. The white paper and the original code can be found here. This code and documentation was found to have errors, but it does provide some documentation that can be used to develop your own sdram controller. Additional information on ram can be found on the following pages:

RAM Guide Good documentation on how ram works.
HULK App Notes The original application notes... since then, the HULK project has evolved into Manticore
Manticore The evolved HULK project

The SDRAM controller basically acts as an interface into the SDRAM. This particular controller has been modified to work with the NIOS Board. The controller is currently interfacing the SODIMM socket with Azenram PC100 128MB. The datasheet for the ram can be found here. The controller is somewhat generic. The controller handles reads, writes, burst mode, and automatically refreshes the ram. It should handle data masking, but this was a feature not used by the group and as such probably not tested very well.

The latest version of their SDRAM has been modified slightly for it to compile in the Quartus II software. The datamask functionality has been removed. The controller has been downloaded and seems to be working. You can download the file:
sdram_control.vhd

Be aware that on simulation you will have to wait for a while for the ram to initialize and be ready to receive commands. A ready signal is asserted once the ram is ready to receive commands.

The read cycle works as follows:

1. The R_enable_I signal is asserted high, for a read command
2. De-asset the R_enable_I signal
3. The address is put on the RW_address_I signal vector and the databus is set to high impedance to allow the ram to overwrite anything on the databus
4. Wait for the ram to send back a ready signal

The write cycle works as follows:

1. The W_enable_I is asserted high, for a write command
2. De-assert the W_enable_I signal
3. The address is put on the RW_address_I signal vector and the data is put on the databus
4. Wait for the ram to send back a ready signal

The above algorithms show only the basic functionality. The commands each send back an acknowledge signal to make sure the ram received the command and they also have a transmit and receive signal that can be used to put the data on the databus.

The current SDRAM controller does not work with the 128 MB ram, due to the timing requirements. The controller can be simulated and it is evident that it is sending the correct signals to the ram but we were unable to make it work. For debugging purposes:
Make sure you are sending a clock to the RAM using pin P5
Make sure you have the correct pins mapped
Make sure simulations are correct
Try to scope the signals sent to the ram
If the ram is set to run at a certain clock frequency you can create a PLL to create the required clock signal
Make sure the ram is getting the correct clock
Make sure the databus is bi-directional
Make sure you are setting the databus to high impedance when you want to read from the ram

For more information contact: lramirezuoa@hotmail.com