--------------------------------------------------------
-- Clock Divider Module
-- EE 552 Project
-- Audio Processing Unit
-- February, 2003
--
-- FILE NAME: clock_divider.vhd
--
-- DESCRIPTION: Generic clock divider module.
--	Performs a two stage clock division
--	using the generics DIVIDER1 and DIVIDER2
--
-- Performs the function:
--	clk_out = clk_in / (4 * DIVIDER1 * DIVIDER2)
--------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library work;
use work.interface.all;

entity Clock_divider is
	Generic(Divider1 : integer := 4;
		Divider2 : integer := 4		
		);
    	Port(	Clk_in:	in std_logic;	--high speed input clock
           	Clk_out:out std_logic	--divided clock output
		);
end Clock_divider;

architecture Behavioral of Clock_divider is
	signal clk_mid, clk_slow : std_logic;
begin

	--first stage of division 
	--sensitive to clk_in
	--counts from 0 to DIVIDER1 then toggles clk_mid
	process (Clk_in)
	variable count : integer range 0 to Divider1;
	begin
		if rising_edge(Clk_in) then
			count := count+1;
			if count = Divider1 then
				count := 0;
--				clk_mid <= not clk_mid;
				if clk_mid = '0' then			--**NOTE
					clk_mid <= '1';			--use the if/then/else structure
				else					--for behavioural simulation as the 
					clk_mid <= '0';			--'NOT' operator will not function correctly
				end if;					--on undefined signals
			end if;
		 end if;
	end process;

	--second stage of division 
	--sensitive to clk_mid
	--counts from 0 to DIVIDER1 then toggles clk_slow
	process (clk_mid)
	variable count_m : integer range 0 to Divider2;
	begin
		if rising_edge(clk_mid) then
			count_m := count_m + 1;
			if count_m = Divider2 then
				count_m := 0;
--				clk_slow <= not clk_slow;
				if clk_slow = '0' then
					clk_slow <= '1';
				else
					clk_slow <= '0';
				end if;
			end if;
		 end if;
	end process;

	Clk_out <= clk_slow;

end Behavioral;