-- This program downsamples the clock


-- Acknowledgements
-- clk_divider1.vhd
-- http://www.ee.ualberta.ca/~elliott/ee552/studentAppNotes/
-- 2000_w/interfacing/ADC_sample_hold/clk_divider1.vhd

library ieee;
use ieee.std_logic_1164.all;
library work;
use work.ADC_pkg.all;

entity clk_divider is
	generic(
		CLOCK_DIV		: positive := 33
	);
	port(
		reset			: in std_logic;
		clk_in			: in std_logic;
		clk_out			: out std_logic
	);
end entity clk_divider;

architecture rtl of clk_divider is

signal clk_temp : std_logic := '0';

begin
	
	clk_out <= clk_temp;

	process(clk_in) is
	variable signal_count	: natural range 0 to CLOCK_DIV := 0;
	begin

		if (reset = '0') then
			signal_count := 0;
		elsif rising_edge(clk_in) then
			signal_count := signal_count + 1;
			if signal_count = CLOCK_DIV then
				clk_temp <= not clk_temp;
				signal_count := 0;
			end if;
		end if;

	end process;


end rtl;