-- file: ad_converter.vhd ------------------------------------- -- control module for the analog to digital converter -- Shauna Rae -- October 29, 1999 -- **Has to be made for 8 bit selection for 7 flex sensors -- **use a 500kHz clock ----------------------------------------- --entity ----------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; library work; --use work.ad_converter_pkg.all --use work.en_register_pkg.all; use work.ADC_pkg.all; entity ad_converter is generic(datawidth: positive:= 8); port (from_adc : in std_logic_vector(datawidth-1 downto 0); --output from ADC adc_dataReady, slow_clk, reset, enable : in std_logic; --EOC, divided clock, reset, acquire adc_select : out std_logic_vector(2 downto 0); --add A,B,C adc_output000, adc_output001, adc_output010, adc_output011, --7 registers for 7 flex sensors adc_output100, adc_output101 : out std_logic_vector(datawidth-1 downto 0); adc_clock, adc_loadAddressStart, adc_outputEnable, data_valid --divided clock o/p, AEL/Start, OE, ... : out std_logic; skip_in: in std_logic; mode, skip_out: out std_logic); end ad_converter; architecture mixed of ad_converter is signal selection: std_logic_vector(2 downto 0); signal count: integer; signal outputEnable, flag_start, flag_wait, loadAddressStart, enable000, enable001, enable010, enable011, enable100, enable101, acq_flag,mode_inter,--new var to stop multi conv/btn data_valid000, data_valid001, data_valid010, data_valid011, data_valid100, data_valid101 : std_logic; begin adc_clock <= slow_clk; adc_loadAddressStart <= loadAddressStart; adc_select <= selection; adc_outputEnable <= outputEnable; test :process(slow_clk, reset) begin -- reset state if reset = '0' then mode <= '1'; -- initialization mode (can write sensor vals to RAM) mode_inter <= '1'; count <= 25; -- 0-25(init mode) 26->(translate) selection <= "000"; flag_start <= '0'; loadAddressStart <= '0'; data_valid <= '0'; -- on rising edge of slow_clk elsif slow_clk'event and slow_clk = '1' then -- data_valid should go high when data from -- all registers is valid, once all four data_valid <= data_valid101; skip_out <= not skip_in; --tells the other component that skip was pressed if count > 25 then --set to translate mode mode <= '0'; mode_inter <= '0'; end if; -- alternate between starting conversion -- and reading output from ADC if ( (flag_start = '0') and ( enable = '0' or (skip_in = '0' and mode_inter = '1') ) and (acq_flag = '0') ) then -- load address and start conversion -- requires a pulse if loadAddressStart = '0' then outputEnable <= '0'; loadAddressStart <= '1'; elsif loadAddressStart = '1' then loadAddressStart <= '0'; flag_start <= '1'; end if; -- now read output elsif flag_start = '1' then -- check if conversion complete -- for even addresses flag_wait should -- be one for odd 0 if flag_wait = '1' and (selection = "000" or selection = "010" or selection = "100") then -- change address if selection = "000" then selection <= "001"; elsif selection = "010" then selection <= "011"; elsif selection = "100" then selection <= "101"; end if; -- set outputEnable high outputEnable <= '1'; -- clear flag to begin next conversion flag_start <= '0'; -- case for odd addresses elsif flag_wait = '0' and (selection = "001" or selection = "011" or selection = "101") then if selection = "001" then selection <= "010"; elsif selection = "011" then selection <= "100"; elsif selection = "101" then selection <= "000"; count <= count + 1; --increment count end if; outputEnable <= '1'; flag_start <= '0'; end if; end if; end if; end process; -- This process is used to check that the a conversion -- is complete on the ADC. This is indicated by a -- rising edge of the adc_dataReady line. check_dataReady : process(adc_dataReady) begin if rising_edge(adc_dataReady) then if flag_wait = '0' then flag_wait <= '1'; elsif flag_wait = '1' then flag_wait <= '0'; end if; end if; end process check_dataReady; --makes sure that 6 conversion cycle done once per acquire button push check_acq_flag : process(data_valid101, enable, skip_in) begin if data_valid101 = '1' then acq_flag <= '1'; elsif enable = '1' and skip_in = '1' then acq_flag <= '0'; end if; end process check_acq_flag; -- store data in appropriate registers by enabling with selection select enable000 <= outputEnable when "001", '0' when others; with selection select enable001 <= outputEnable when "010", '0' when others; with selection select enable010 <= outputEnable when "011", '0' when others; ---- additional enables with selection select enable011 <= outputEnable when "100", '0' when others; with selection select enable100 <= outputEnable when "101", '0' when others; with selection select enable101 <= outputEnable when "000", '0' when others; -- assign the outputs of the converter to an enabled register inregister000 : en_register generic map ( data_width => 8) port map( -- inputs clock => slow_clk, reset => reset, enable_in => enable000, register_in => from_adc, -- outputs register_out => adc_output000, enable_out => data_valid000); inregister001 : en_register generic map ( data_width => 8) port map( -- inputs clock => slow_clk, reset => reset, enable_in => enable001, register_in => from_adc, -- outputs register_out => adc_output001, enable_out => data_valid001); inregister010 : en_register generic map ( data_width => 8) port map( -- inputs clock => slow_clk, reset => reset, enable_in => enable010, register_in => from_adc, -- outputs register_out => adc_output010, enable_out => data_valid010); inregister011 : en_register generic map ( data_width => 8) port map( -- inputs clock => slow_clk, reset => reset, enable_in => enable011, register_in => from_adc, -- outputs register_out => adc_output011, enable_out => data_valid011); --------------------------------------------- Additional 3 registers inregister100 : en_register generic map ( data_width => 8) port map( -- inputs clock => slow_clk, reset => reset, enable_in => enable100, register_in => from_adc, -- outputs register_out => adc_output100, enable_out => data_valid100); inregister101 : en_register generic map ( data_width => 8) port map( -- inputs clock => slow_clk, reset => reset, enable_in => enable101, register_in => from_adc, -- outputs register_out => adc_output101, enable_out => data_valid101); end mixed;