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--ADC controller- **so far just passes it a slower clock and dbncd buttons**
-----------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
library work;
use work.ADC_pkg.all;
use work.SLG_pkg.all;
--use work.ad_converter_pkg.all;

entity ADController is
	generic(datawidth: positive:= 8);
	port(
		clock: std_logic; --the regular 33.3 MHz clock
		datain: in std_logic_vector(datawidth-1 downto 0);	-- Output data from ADC(Din)
		reset: in std_logic;			-- reset for whole system(rst)
		acquire: in std_logic;			-- indicate if sample is needed and when data is not needed(ack)
		ALE_start: out std_logic;             -- enable line for ADC channel select and start conv signal
		EOC: in std_logic;				-- tells if Data in the register is valid (DataRdy)
		sel: out std_logic_vector(2 downto 0); --sel selects which channel ADC will convert
		clk_ADC: out std_logic;				-- the slower clock 640 kHz for the ADC
		d1: out std_logic_vector(datawidth-1 downto 0);
		--d2,d3,d4,d5,d6: out std_logic_vector(datawidth-1 downto 0); -- Sampled Data(Dout)
		data_valid: out std_logic;
		OE: out std_logic;
		skip_in: in std_logic;
		mode, skip_out: out std_logic
		
		);
end ADController;


architecture behavioural of ADController is

signal dout_inter, d2,d3,d4,d5,d6: std_logic_vector(datawidth-1 downto 0);
signal debounced_reset, debounced_acq, debounced_skip, tmp, clk_inter : std_logic;

begin

tmp <= '1';

slower_clock: clk_divider 
	generic map( CLOCK_DIV => 67)
	port map(
		reset => tmp,
		clk_in => clock,			
		clk_out	=> clk_inter		
	);

reset_deb: debouncer
	generic map( CLOCK_DIV => 50)
	port map( 
		clock => clk_inter,		
		reset => tmp,		
		signal_in => reset,		
		signal_out => debounced_reset		
	);

acquire_deb: debouncer
	generic map( CLOCK_DIV => 50)
	port map(
		clock => clk_inter,			
		reset => tmp,			
		signal_in => acquire,		
		signal_out => debounced_acq
	);

skip_deb: debouncer
	generic map( CLOCK_DIV => 50)
	port map(
		clock => clk_inter,			
		reset => tmp,			
		signal_in => skip_in,		
		signal_out => debounced_skip
	);

A2D: ad_converter
	port map(from_adc => datain,
				adc_dataReady => EOC,
				slow_clk => clk_inter,
				reset => debounced_reset,
				enable => debounced_acq,
				adc_select => sel,
				adc_output000 => dout_inter, 
				adc_output001 => d2, 
				adc_output010 => d3, 
				adc_output011 => d4, 
				adc_output100 => d5, 
				adc_output101 => d6, 
				adc_clock => clk_ADC,
				adc_loadAddressStart => ALE_start,
				adc_outputEnable => OE,
				data_valid => data_valid,
				skip_in => debounced_skip,
				mode => mode, 
				skip_out => skip_out
	);


d1 <= not dout_inter;

end behavioural;