-- ADC_pkg.vhd
----------------------
-- ADC package
----------------------
-- this is the package of the ADC0809
----------------------

library ieee;
use ieee.std_logic_1164.all;

package ADC_pkg is

component ADController is
	generic(datawidth: positive:= 8);
	port(
		clock: std_logic; --the regular 33.3 MHz clock
		datain: in std_logic_vector(datawidth-1 downto 0);	-- Output data from ADC(Din)
		reset: in std_logic;			-- reset for whole system(rst)
		acquire: in std_logic;			-- indicate if sample is needed and when data is not needed(ack)
		ALE_start: out std_logic;             -- enable line for ADC channel select and start conv signal
		EOC: in std_logic;				-- tells if Data in the register is valid (DataRdy)
		sel: out std_logic_vector(2 downto 0); --sel selects which channel ADC will convert
		clk_ADC: out std_logic;				-- the slower clock 640 kHz for the ADC
		d1,d2,d3,d4,d5,d6: out std_logic_vector(datawidth-1 downto 0); -- Sampled Data(Dout)
		data_valid: out std_logic;
		OE: out std_logic;
		skip_in: in std_logic;
		mode, skip_out: out std_logic
		);
end component ADController;


component ad_converter
	generic(datawidth: positive:= 8);
	port (from_adc : in std_logic_vector(datawidth-1 downto 0);
			adc_dataReady: in std_logic;
			slow_clk: in std_logic;
			reset: in std_logic;
			enable : in std_logic; --enable is the button
			adc_select : out std_logic_vector(2 downto 0);
			adc_output000, adc_output001, adc_output010, 
			adc_output011, adc_output100, adc_output101
			: out std_logic_vector(datawidth-1 downto 0);
			adc_clock: out std_logic;  
			adc_loadAddressStart: out std_logic;
			adc_outputEnable: out std_logic;
			data_valid: out std_logic;
			skip_in: in std_logic;
			mode, skip_out: out std_logic);
	end component;


	component en_register is
		generic (data_width : positive := 20);
        port(clock, reset, enable_in : in std_logic; 
			enable_out: out std_logic;
            register_in: in std_logic_vector(data_width-1 downto 0);
            register_out : out std_logic_vector(data_width-1 downto 0));
    end component en_register;

    component multiplex is
		generic (data_width : positive := 16);
        port(select_line : in std_logic; 
            in_a, in_b: in std_logic_vector(data_width-1 downto 0);
         	output : out std_logic_vector(data_width-1 downto 0));
   	end component multiplex;

	component nregister is
		generic (data_width : positive := 16);
        port(clock, reset : in std_logic; 
            register_in: in std_logic_vector(data_width-1 downto 0);
            register_out : out std_logic_vector(data_width-1 downto 0));
    end component nregister;


end package ADC_pkg;