Group Members: Chris Lee, Michael Mah, Jaffer Kapasi, Dave Yeung
E-mails: ccl1@ualberta.ca, mwmah@ualberta.ca, jkapasi@ualberta.ca, dkyeung@ualberta.ca
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In this tutorial, you will learn to use Quartus II to synthesize a VHDL design, extract timing and performance information, simulate your design, and configure your FPGA.

Compiling with Quartus

The first thing that must be done to synthesize a design is to create a new project.  Do this by selecting:

        (toolbar) File -> New Project Wizard

Work through this wizard to create your top-level design entity, to add files to your project, and to select your device.  Note: When you are adding your files to the project, the order in which the file names appear matter!  They must appear in the order of compilation.  Also, you do not need to add all files in your project; you only need to add packages, which your top-level entity requires, and the top-level entity itself.  Quartus will automatically find your components in your design hierarchy as long as the VHDL files are in your working directory.

Once you have created your project, you can compile it by clicking the Start Compilation button or:

        (toolbar) Processing -> Start Compilation

After the compilation is finished, a compilation report pops up.  In this compilation report, you can find:
Messages - useful for correcting compiler errors and to see warning messages.
Hierarchy - shows a diagram of your design hierarchy.
Resource Utilization - find logic cells, pins, memory bits, etc.
Timing Analyses - find maximum frequency, setup/hold times, critical path, etc.

Simulating with Quartus

Once you have successfully compiled your project, you can create a new simulation by selecting:

        (toolbar) File -> New

        Click on the Other Files tab and select Vector Waveform File.

You can add nodes in your design by:

        (toolbar) Edit -> Insert Node or Bus

        Click Node Finder

In the Filter drop down list, select Pins: all if you only want the see pins in your design.  You can select more advanced nodes by selecting different options in the drop down list.

Click OK after you select all the nodes you wish to display and they will now be shown on the waveform.

Note: You can change the end time of your simulation by:

        (toolbar) Edit -> End Time

When you are ready to run your simulation, simply click the Run Simulation button or:

        (toolbar) Processing -> Run Simulation

After Quartus finishes the simulation, a simulation report pops up with the results.

Configuring your FPGA

Before you can download your project to your FPGA, you must assign the necessary pins.  Click:

        (toolbar) Assignments -> Assign Pins

        Select a Pin Number and its corresponding Pin Name.  Click Add.

You have just assigned one pin of your project.  Repeat these steps to assign all of your I/O pins.

Note: You may find this process very slow and boring.  There is a much faster way of performing your pin assignments.  The following application note describes this process.  http://www.ee.ualberta.ca/~elliott/ee552/studentAppNotes/2003_w/cad/quartus_pin_assignments/quartus_pin_assignments.htm

This link basically describes how you can assign your pins via a .csf file.

You should now be ready to download your project to your FPGA.  Recompile your project so that it includes your pin assignments.  Click:

        (toolbar) Tools -> Programmer

        Click Add File.

        Select your project's .sof file.

        Click Start.

Congratulations!!  You have successfully completed your project!!

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Group Members: Chris Lee, Michael Mah, Jaffer Kapasi, Dave Yeung
E-mails: ccl1@ualberta.ca, mwmah@ualberta.ca, jkapasi@ualberta.ca, dkyeung@ualberta.ca
Last Modified: 2003-03-25