This document will take you through a step by step procedure of creating, compiling, simulating and implementing a VHDL design using Xilinx ISE tools.
Contents
Introduction
Project Navigator is the main user interface for the Xilinx ISE software. Project Navigator helps the user with design entry, compilation, pin assignment, etc. Multiple source code files can be combined, edited and debugged from within Project Navigator using editors and devices can be associated with projects. The logic design flow is represented for FPGA and CPLD implementation and graphic flags are set indicating where problems have occurred.
Back to top
Download the software
The Xilinx ISE Webpack can be downloaded from the following link
http://www.xilinx.com/webpack/index.htm
Back to top
Here is a step by step procedure for creating a new design.
- Open the 'Xilinx Project Navigator'. Select File - > New Project
- In the New Project dialog box, type the desired location in the Project Location field, or browse to the directory under which you want to create your new project directory using the browse button.Give your project a meaningful name. A subdirectory by that name is automatically created in the directory path in the Project.
- Use the pull-down arrow to select the Value for each Property Name. Click in the field to access the pull-down list. Change the values as follows:
Device Family: Spartan 2
Device: the device you are using
Design Flow: XST VHDL
Click OK
- Next step is to add new files to your design.You can either import existing VHDL files into your design or create new files.
Importing existing files : Select Project -> Add Source. Select the file you wish to add to the design and click OK.Creating new files : Select Project -> New Source. Select 'VHDL Module' and specify filename and click OK.
Next step is creating your design. In other words- start coding !!
Compiling and Synthesizing
On the left of the screen, you will see two windows. One of these is "Sources in Project" and the other is "Processes for Current Sources". (You can enable them under View if not visible). Expand the "Synthesize" heading and double-click on "Check Syntax". To compile all the files in the design, double-click on "Analyze All". Watch the log window at the bottom of the screen to check whether the design compiled successfully or not. If the compilation is successful, then a green check will appear. Otherwise if there are errors, then a red cross mark will appear. Double click on the error messages displayed to go to line containing the error.
Simulating
Use ModelSim Simulator for simulating your design. Click below to find out how to use ModelSim.Pin Assignments
- Under the "Design Entry Utilities" in the "Processes for Current Source" window, expand the "User constraints Tab". Double-click on the second selection " Edit Implementation Constraints (Constraints Editor)". Click on the ports tab and enter the location of each I/O pin in your desing. For example enter p23. After you are done entering all the I/O pins, click on the save icon and close the window.
Back to top
- Double click on the "Implement Design" in the "Processes for the Current Source" window. Watch the log window for any errors or warnings.
Downloading to the FPGA
- If the implementation completes successfully, you are ready to download the design to the FPGA.
- Expand the "Generate Programming File" heading and double click on the "Configure Device". This will generate the .bit file which will be downloaded to the FPGA.
- Double click on the GXSLOAD tool on the desktop ( or select it from the start menu). Next select the parallel port that your XS board is connected to from the Port pull down menu. Then select the type of XS board you are using from the Board Type pulldown list.
- Then, download the .BIT file by simply dragging it to the FPGA/CPLD column of the GXSLOAD window.
- Click on the 'Load' button to begin sending the file to the FPGA. The .BIT file contains the configuration bitstreams that are loaded into the FPGA. GXSLOAD will reject any non-downloadable files.
- The link to the manual for the tools is given below
http://www.xess.com/manuals/xstools-v4_0.pdfBack to top